SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
The analysis of the design, and the performance assessment of the Orbiter S-band communication equipment are reported. The equipment considered include: network transponder, network signal processor, FM transmitter, FM signal processor, payload interrogator, and payload signal processor.
A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.
The distributed processing concept is defined in terms of control primitives, variables, and structures and their use in performing a decomposed discrete Fourier transform (DET) application function. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common database by employing control primitives. Access to selected areas within the common database is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks are also described. The experimental hardware configuration consists of IMSAI 8080 chassis which are independent, 8 bit microcomputer units. These chassis are linked together to form a multiple processing system by means of a shared memory facility. This facility consists of hardware which provides a bus structure to enable up to six microcomputers to be interconnected. It provides polling and arbitration logic so that only one processor has access to shared memory at any one time.
This paper comprises a description of Synthetic Aperture Radar (SAR) processing approaches and a discussion on the processor complexity measures. The objective of the paper is to provide basic system knowledge on the design of a real-time signal processor for spaceborne synthetic aperture radar. A review of SAR sensor performance capability and general electronic processing approaches will be given first. The discussion of SAR processor complexity is divided into two areas: the arithmetic complexity and the control complexity. A generalized treatment of these subjects is provided. The results could be readily extended to special cases.
The applicability of parallel processing schemes to the implementation of a contextual classification algorithm which exploits the spatial and spectral context of a multispectral remote sensing pixel to achieve classification is examined. Two algorithms for classifying each multivariate pixel taking into account the probable classifications of neighboring pixels are presented which make use of a size three horizontally linear neighborhood, and the serial computational complexity of the more efficient algorithm is shown to grow in proportion to the number of pixels and the cube of the number of possible categories. The implementation of the more efficient algorithm on a CDC Flexible Processor system and on a multimicroprocessor system such as the proposed PASM is then discussed. It is noted that the use of N processors to perform the calculations N times faster than a single processor overcomes the principal disadvantage of contexual classifiers, i.e., their computational complexity.
The SPAR thermal analyzer, a system of finite-element processors for performing steady-state and transient thermal analyses, is described. The processors communicate with each other through the SPAR random access data base. As each processor is executed, all pertinent source data is extracted from the data base and results are stored in the data base. Steady state temperature distributions are determined by a direct solution method for linear problems and a modified Newton-Raphson method for nonlinear problems. An explicit and several implicit methods are available for the solution of transient heat transfer problems. Finite element plotting capability is available for model checkout and verification.
The programmable pilot oriented display (P-POD), a multiprocessor based flight information processing and display unit, is discussed. Communication protocols between the three Z-80 processors inside P-POD are reviewed. The interface between the video processor, P2, and the main processor, P1, was tested. Hardware and software were revised. Data flow between P1 and P2 is illustrated. While running diagnostic routines to exercise the P1/P2 interface at maximum speed an intermittent failure was observed. A check of possible noise sources or race conditions in the hardware did not reveal the source of this failure. Possible software timing problems were also fully investigated. To eliminate the effects of this type of failure a performance monitor routine was used to detect these occasional failures and correct them. The data transmission cycle between P1/P2 is either allowed to continue normal operation or is re-initialized and restarted when an error is detected.
To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.
The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.
A data highway terminal controller with transmission controllers assigned to each processor in a set of multiple processors is described. Shared-use terminals are loop connected to the processors via the controllers.
Digital image processing for geological applications will be integrated with geographic information systems and data base management systems. While multiband data sets from radar and multispectral scanners will make extreme demands on memory, bus and processor architectures, it is expected that array processors and VLSI/VHSIC dedicated function chips will allow the use of fast Fourier transform and classification algorithms. It is anticipted that, as processor power increases, the weakest link of a processing system will become the analyst who uses it. Human engineering of systems is therefore recommended for the most effective utilization of remotely sensed geologic data.
A review of the thruster/power-processor-interface requirements for (mercury and inert gas) ion-thrusters, an evaluation of various approaches to simplifying the power-processor circuitry, and the test results of the recently developed 8-cm mercury-ion-thruster simplified power-processor unit (SPPU) are presented. The SPPU demonstrates the feasibility of stable thruster operation using highly simplified power-processing techniques and achieves an approximately tenfold reduction in the electronic parts count when compared to the existing power-processor unit (PPU) used in the Hughes/NASA Lewis Research Center 8-cm-diameter (mercury) Ion Auxiliary Propulsion Subsystem (IAPS).
A systems configuration for the baseband processor for a TDMA communications satellite utilizing the 30 GHz uplink and 20 GHz downlink bands will be discussed. The baseband processor functions include QPSK burst demodulation, convolutional decoding, data routing, encoding, QPSK modulation, and antenna steering. The performance of the burst demodulator will be examined. Power and weight estimates for the baseband processor will be presented.
The combination of a strap-down analog sun acquisition sensor (AS) and an on-board digital programmable signal processor results in a versatile guidance and control system. The combination can orient the rotation axis of a spin-stabilized spacecraft to the sun no matter what the initial attitude of the spacecraft. During the sun orientation process, spacecraft spin rate can be sensed and supplied as an input to the control algorithm. If needed, the AS-signal processor combination can be used to perform a rhumb-line turn maneuver. In case of unexpected spacecraft operating conditions, or unplanned pointing directions, the signal processor program can be updated via earth-based transmission of another program to cover the new situation. Using only three radiation-hard cadmium-sulfide detectors, containing no moving parts, needing only a few microwatts of power, included in a volume of 550 cubic cm (a redundant pair), and weighing only 540 grams, the AS is a small, simple, sturdy sensing device.
The development of novel electro-optic spatial light modulators (both one and two dimensional) which allows real-time coherent optical SAR processors to be implemented is outlined. It is suggested that the availability of such processors may initiate new mission applications not presently envisioned due to current digital processor limitations.
The philosophy and data encoding possible in systolic array optical processor (SAOP) were reviewed. The multitude of linear algebraic operations achievable on this architecture is examined. These operations include such linear algebraic algorithms as: matrix-decomposition, direct and indirect solutions, implicit and explicit methods for partial differential equations, eigenvalue and eigenvector calculations, and singular value decomposition. This architecture can be utilized to realize general techniques for solving matrix linear and nonlinear algebraic equations, least mean square error solutions, FIR filters, and nested-loop algorithms for control engineering applications. The data flow and pipelining of operations, design of parallel algorithms and flexible architectures, application of these architectures to computationally intensive physical problems, error source modeling of optical processors, and matching of the computational needs of practical engineering problems to the capabilities of optical processors are emphasized.
In order to handle arbitrary-sized matrices with fixed-sized optical matrix processors, it is necessary to expand or contract the problem to fit the processor. This preprocessing is examined. It is applied to the type of triple-matrix product calculation needed for Kalman filtering. Emphasis will be placed on systolic-type processors.
A rapid computation of a sequence of transonic flow solutions has to be performed in many areas of aerodynamic technology. The employment of low-cost vector array processors makes the conduction of such calculations economically feasible. However, for a full utilization of the new hardware, the developed algorithms must take advantage of the special characteristics of the vector array processor. The present investigation has the objective to develop an efficient algorithm for solving transonic flow problems governed by mixed partial differential equations on an array processor.