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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,207 records · Page 67
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Optimal design of two-qubit quantum circuits

In order to demonstrate non-trivial quantum computations experimentally, such as the synthesis of arbitrary entangled states, it will be useful to nderstand how to decompose a desired quantum computation into the shortest possible sequence of one-qubit and two-qubit gates. We contribute to this effort by providing a method to construct an optimal quantum circuit for a general two-qubit gate that requires at most 3 CNOT gates and 15 elementary one qubit gates. We then prove that these constructions are optimal with respect to the family of CNOT, y-rotation, z-rotation, and phase gates.

quantum circuit unitary operation↗
NASA NTRS2005

Novel design of an all-cryogenic RF pound circuit

We report on the design, construction and test of a new all-cryogenic RF Pound circuit used to stabilize a 100 MHz VCXO. Here, all active and passive RF components used to accomplish the phase modulation and detect a PM to AM conversion have been installed into the cryogenic environment.

sapphire↗
NASA NTRS2007

Designing High Speed Printed Circuit Boards Using DxDesigner and Expedition

Mentor's DxDesigner and Expedition schematic capture and printed circuit board tools were chosen to implement a custom high speed signal processing board containing many high pin count Field Programmable Gate Arrays and many high speed serial connections with data rates over 2 Gigasamples/sec. The methodology used to place the parts and route the board involved the interaction of both the DxDesigner and Expedition tools. The basic design philosophy was to specify as much as possible through design constraints at the schematic level. This paper will explore implementing that philosophy in both tools to facilitate part placement and trace routing.

printed circuit boards↗
NASA NTRS2016

An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it uses GPUs built in 28 nm technology and achieves about 1000 pJ. Correlators being designed for the SKA telescopes (N = 128 and N = 512) using FPGAs in 16nm technology are predicted to achieve about 100 pJ.

ASIC↗
NASA NTRS2016

Effects of Parasitic Reactance on Lattice Circuit Slotline Switch

A slotline lattice switch has recently been proposed and demonstrated. In that paper, ideal diode characteristics were assumed. In this paper, the effects of parasitic reactances, due to the diode and the wire bonds that connect it to the circuit, are investigated. The switch is compared to a traditional slotline switch with a single diode across the slot.

pin diode↗
NASA NTRS2016

Effects of Parasitic Reactance on Lattice Circuit Slotline Switch

A slotline lattice switch has recently been proposed and demonstrated. In that paper, ideal diode characteristics were assumed. In this paper, the effects of parasitic reactances, due to the diode and the wire bonds that connect it to the circuit, are investigated. The switch is compared to a traditional slotline switch with a single diode across the slot.

Lattice Circuit↗
NASA NTRS2018

Comparing and Integrating Constraint Programming and Temporal Planning for Quantum Circuit Compilation

Recently, the makespan-minimization problem of compiling a general class of quantum algorithms into near-term quantum processors has been introduced to the AI community. The research demonstrated that temporal planning is a strong solution approach for the studied class of quantum circuit compilation (QCC) problems. In this paper, we explore the use of methods from operations research, specifically constraint programming (CP), as an alternative and complementary approach to temporal planning. We also extend previous work by introducing two new problem variations that incorporate important characteristics identified by the quantum computing community. We apply temporal planning and CP to the baseline and extended QCC problems as both stand-alone and hybrid approaches. The hybrid method uses solutions found by temporal planning to warm-start CP, leveraging the ability of temporal planning to find satisficing solutions to problems with a high degree of task optionality, an area that CP typically struggles with. These solutions are then used to seed the CP formulation which significantly benefits from inferred bounds on planning horizon and task counts provided by the warm-start. Our extensive empirical evaluation indicates that while stand-alone CP is not competitive with temporal planning, except for the smallest problems, CP in a hybrid setting is beneficial for all temporal planners in all problem classes.

quantum circuit compilation↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS2021

Probing the Origin of the Open Circuit Voltage in Perovskite Quantum Dot Photovoltaics

Perovskite quantum dots (PQDs) have many properties that make them attractive for optoelectronic applications, including expanded compositional tunability and crystallographic stabilization. While they have not achieved the same photovoltaic (PV) efficiencies of top-performing perovskite thin films, they do reproducibly show high open circuit voltage (VOC) in comparison. Further understanding of the VOC attainable in PQDs as a function of surface passivation, contact layers, and PQD composition will further progress the field and may lend useful lessons for non-QD perovskite solar cells. Here, we use photoluminescence-based spectroscopic techniques to understand and identify the governing physics of the VOC in CsPbI3 PQDs. In particular, we probe the effect of the ligand exchange and contact interfaces on the VOC and free charge carrier concentration. The free charge carrier concentration is orders of magnitude higher than in typical perovskite thin films and could be tunable through ligand chemistry. Tuning the PQD A-site cation composition via replacement of Cs+ with FA+ maintains the background carrier concentration but reduces the trap density by up to a factor of 40, reducing the VOC deficit. These results dictate how to improve PQD optoelectronic properties and PV device performance and explain the reduced interfacial recombination observed by coupling PQDs with thin-film perovskites for a hybrid absorber layer.

perovskite quantum dot↗
NASA NTRS2023

An Examination of Heavy Ion-Induced Persistent Visual Error Signatures in an Electronic Display Driver Integrated Circuit

Heavy ion irradiation of a display driver integrated circuit (DDIC) was performed, and persistent visual error signatures were captured. Based on the heavy ion results, error signatures were localized to configuration registers motivate potential mitigation techniques and observations relating to single event effect susceptibility. DDICs serve as an integral component of integrated display systems that will require the development of single event effects test methodologies in anticipation of extensive use in crewed spacecrafts outside of the Earth’s geomagnetic protection.

Electronic Displays↗
NASA NTRS2021

Experimental Data on Open Circuit Voltage Characterization for Li-Ion Batteries

In this article, we present the datasets collected from nine different Li-ion batteries. These datasets contain voltage, current and time measurements during a full charge-discharge cycle of a battery at very low current (that is nearly at �/30 rate). Such low current rate data is suitable for open circuit voltage characterization. The collection of this data was done through the use of an Arbin battery cycler and a thermal chamber was used to control the test temperature. Data were collected over a wide range of temperatures from −25∘C to 50∘C.

Battery management system↗
DOE OSTI2020

Formulation, Design and Experimental Verification of an Open Circuit Electro-Hydraulic Actuator

With the recent electrification trend in the fluid power area, more research has been incentivized to the proposal of cost-effective and energy-efficient solutions for hydraulic systems. Hence, electro-hydraulic actuator (EHA) architectures receive increasing attention. The paper proposes a novel open-circuit EHA architecture, with the goal to obtain a cost-effective mobile solution while maximizing the overall system efficiency. The proposed EHA is capable of meeting or exceeding traditional off-road machine performance, therefore enabling further electrification of off-road machines. Four-quadrant functionality, covering the full speed range, is achieved by a combination of a variable electro-hydraulic drive and valves with different functions and is validated by numerical as well as experimental methods. Here, a simulation model based on the Amesim environment and a dedicated test setup was developed to verify the performance. The good match between simulation and experimental results confirms the potential of the formulation approach of the proposed EHA for applications with different duty cycles and power levels.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

Autonomous Microgrid Restoration Using Grid-Forming Inverters and Smart Circuit Breakers: Preprint

The proliferation of distributed inverter-based resources (IBRs) raises the questions if these IBRs can be used to blackstart microgrids and distribution feeders after major outages. In this paper, we propose and evaluate an autonomous microgrid restoration concept using grid-forming (GFM) IBRs and smart circuit creakers (SCBs). The concept is first explored in simulation platform and then a hardware testbed containing actual GFM inverters is developed to demonstrate these functionalities. A combination of dispatchable virtual oscillator control (dVOC) and droop-based control schemes have been designed for GFM inverter controls in the software simulations and hardware testbed. Subsequently, operation of SCBs using two distinct principles have been demonstrated that can restore or connect portions of the network.

grid reconfiguration↗
DOE OSTI2024

Investigation of a Multi-Rotor Triboelectric Nanogenerator Using a Modular Flexible Circuit Board Stack

Triboelectric nanogenerators (TENGs) are a nascent class of energy harvester that are being explored for scavenging energy from small ocean waves. To date, they have been integrated in wave energy converters (WECs) designed to capture random motion caused by the perturbations of the ocean surface. Blue economy applications such as ocean observation can benefit greatly from more substantial wave-derived power, as such, the power output of existing TENG WECs must be increased several-fold to become viable. This study describes the conceptualization of a rotary TENG, and the subsequent efforts to increase its power output by stacking multiple stator and rotor pairs. In the latter part of this study, we introduce a novel means of incorporating a friction element into the design of the TENG by employing flexible printed circuit board (PCB) rotors. At rest, these flexible rotors will contact the stator, building static charges due to friction, at speed, these flexible rotors will be decoupled from the stator, reducing friction and allowing faster rotation. Initial results indicate that the power output of the flexible PCB rotor does not produce more power than a rigid, acrylic disk rotor, however the current output of the prototype is boosted, and the prototype is far more compact, allowing for a higher energy density than the rigid rotor prototype.

bench testing↗