A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS
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Wen, Xianshan↗
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H ∞ Control for Energy Dispatch in Autonomous Nanogrid With Communication Delays
This paper proposes an optimal controller and estimator for energy dispatch to balance the power supply and demand considering communication delays. The proposed algorithm involves modeling an autonomous nanogrid (ANG) consisting of distributed energy resources, energy storage systems, loads, an $H$ ∞ controller with a reference power modulation technique, and a state estimator. The ANG was developed to express the dynamic supply-demand energy balance of a nanogird system. Reference power modulation was designed to generate the desired ESS power based on the imbalanced energy. Random communication delays were modeled using a stochastic variable satisfying the Bernoulli random binary distribution. The optimal $H$ ∞ controller and estimator were developed using a linear matrix inequality approach to exponentially stabilize the closed-loop system. Simulations were performed using real daily demand forecasts obtained from the Korea Meteorological Administration to demonstrate the effectiveness of the proposed real-time optimization algorithm.
24 POWER TRANSMISSION AND DISTRIBUTION↗
Review of Challenges and Research Opportunities for Control of Transmission Grids
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24 POWER TRANSMISSION AND DISTRIBUTION↗
A 2.1 GS/s 2-Channel Pipeline-SAR ADC With Speed-Enhanced Bootstrap Switch and Low-Latency SAR Logic
Not Available
Fu, Tao [Department of Electrical and Computer Eng↗
Extended State Observer-Based Robust Model Predictive Velocity Control for Permanent Magnet Synchronous Motor
This article proposes an extended state observer based robust model predictive velocity control to decrease system prediction error under parameter uncertainties for permanent magnet synchronous motor (PMSM). We develop a new PMSM model that consists of velocity and acceleration to lump the system information and an external disturbance into a disturbance. The extended state observer (ESO) is designed to estimate the velocity, acceleration, and disturbance. By estimating the state variables and disturbance using the ESO, the model predictive control (MPC) finds the optimal control input by predicting future system behavior. Additionally, the direct current controller is designed so that the direct current converges to zero. Because the proposed method is not designed based on the cascade structure from the viewpoint of velocity control, the optimization control for the velocity and currents can be defined. Thus, the proposed method is robust against external disturbances and parameter uncertainties owing to feedback linearization, state feedback, and ESO-based MPC using the acceleration PMSM model. The proposed control algorithm was experimentally verified and it showed improved velocity tracking performance compared with ESO-based MPC using the conventional PMSM model.
42 ENGINEERING↗
Observer-Based Nonlinear Control Scheme to Reduce Oscillations and Zero Crossing in Skid-Steer Vehicles
Motion sickness is a common condition experienced by drivers of skid-steer vehicles, primarily caused by zero crossing and oscillations in undamped systems. This study proposes an observer-based nonlinear control scheme to reduce transient oscillations and zero-crossing phenomena in skid-steer vehicles, thereby potentially alleviating motion sickness. Reducing transient oscillations and zero crossing in the transient response may alleviate motion sickness. A nonlinear damping controller is designed to improve transient response by reducing oscillations and zero-crossing. To design the controller, a reduced-order kinematic model based on coordinate transformation is developed. This transformation not only converts the system modeling into a controllable form but also enhances control performance. Modeling error is addressed by considering the distance between the center of the vehicle and the sensor location. Despite these improvements, model uncertainties and external disturbances remain, which may degrade control performance. To ensure robustness and estimate such disturbances, a high-order sliding mode observer (HOSMO) is incorporated. The effectiveness of the proposed method is validated through MATLAB/Simulink and TruckMaker simulations. From the simulation results, it was shown that the proposed method reduced the mean squared error of the tracking error to within 10 % compared to the state feedback controller with the HOSMO.
Seo, Jiwon [Chung-Ang University, Seoul (Korea, Re↗
High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors
Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.
Zhang, Zheyu↗
Common-mode noise reduction with impedance balancing in DC-fed motor drives
Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.
Chen, Ruirui↗
Common-mode inductor saturation analysis and design optimization based on spectrum concept
Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.
Chen, Ruirui↗
Design of a Single Controller for Multiple Paralleled Inverters
Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.
Niu, Jiahao↗
Coupled Inductor Design for Interleaved Three-level Active Neutral Point Clamped Inverters Considering EMI Noise Reduction
This paper presents the coupled inductor design for interleaved three-level active neutral point clamped (ANPC) inverter considering electromagnetic interference (EMI) noise reduction. Compared to two-level case, the scenarios involved in the three-level space vector modulation (SVM) are more complicated when analyzing the volt-seconds of the coupled inductor for paralleled three-level inverter. At system level, the purpose of converter interleaving is to reduce EMI noise and ripple current in most applications, and coupled inductor design should consider the needs of EMI noise reduction and EMI filter design. These issues are discussed in this paper. The relationship between circulating current and EMI noise is illustrated. EMI filter corner frequency as a function of interleaving angle is analytically derived, and optimal interleaving angle for maximum common-mode (CM) filter and differential-mode (DM) filter corner frequencies is discussed. Coupled inductor design methodology for interleaved three-level inverters with SVM is then presented. Experiments on two interleaved ANPC inverters are conducted. The results verify the coupled inductor design. With the derived optimal interleaving angle, the CM and DM EMI noise are significantly reduced.
Chen, Ruirui↗
Analytical Analysis of Ac and Dc Side Harmonics of Three-level Active Neutral Point Clamped Inverter with Space Vector Modulation
This paper presents a comprehensive analytical analysis of the ac and dc side harmonics of the three-level active neutral point clamped (ANPC) inverter with space vector modulation (SVM) scheme. An analytical model to calculate the harmonics of a three-level converter with SVM is developed. The ac side output voltage harmonics and dc side current harmonics characteristics are calculated and analyzed. With the developed models, the impact of interleaving on both sides harmonics are studied which considers the modulation index, interleaving angle, and power factor. The analysis provides guideline for interleaving angle optimization to reduce the ac side power filter and dc side dc-link capacitor. The relationship between electromagnetic interference (EMI) filter corner frequency and switching frequency is also analytically derived which provides guideline for switching frequency and EMI filter design optimization. Two paralleled three-level ANPC inverters are constructed and experimental results are presented to verify the analytical analysis.
Chen, Ruirui↗
Analysis of Circulating Harmonic Currents in Paralleled Three Level ANPC Inverters using SVM
In paralleled voltage source inverters (VSI), circulating current has both high frequency and low frequency components, and its spectrum highly depends on the modulation scheme. Previous research has mostly focused on the circulating current suppression for paralleled two-level VSIs. Little literature exists on similar analysis for paralleled three-level VSIs using space vector modulation. A detailed circulating current spectrum on full frequency range has not been well developed. This paper presents an improved analytical model for three-level space vector modulation (SVM), considering the impacts of regularly sampled reference and dead time. Then, circulating harmonic currents are determined across the full frequency range for various interleaving angles of two three-level ANPC inverters. The calculated harmonics are also verified by experimental results.
Niu, Jiahao↗
Design of an EMF Suppressing Magnetic Shield for a 100-kW DD-Coil Wireless Charging System for Electric Vehicles
This study investigates the electromagnetic field (EMF) emissions of a 100-kW Double-D (DD) wireless charging system (WCS). A shielding technique is proposed to suppress the magnetic field emissions below the limits set by the International Commission on Non-Ionizing Radiation Protection (ICNIRP). The leakage pattern produced by the DD coil is different than unipolar (circular, rectangular, etc.) pads and traditional eddy current based aluminum shields are not effective at suppressing this leakage field. Therefore, a methodically designed magnetic shield could be more effective. This study proposes a shielding technique for DD coils using a combination of aluminum shielding and a low reluctance magnetic shield to suppress the magnetic field emissions. The shielding effectiveness is evaluated through finite element analysis (FEA) models and tested experimentally. The effectiveness of the proposed magnetic shielding and the limits of the conventional aluminum shielding are studied. A prototype 11-kW DD coil wireless charging system is used to experimentally validate the proposed shielding technique. The experimental results show that the aluminum shield increases the emissions of DD coils by 25% and the proposed magnetic shield can be employed to suppress the emission by 60%.
Mohammad, Mostak↗
Modeling, Design, and Experimental Verification of a WPT Level-3 Wireless Charger with Compact Secondary Coupler
This study introduces a wireless power transfer (WPT) Level-3 rated charger with >11 kW nominal output. The proposed system is interoperable for WPT Level-1, 2, and 3 charger applications of which power levels and airgap separations are defined in SAE J2954. The system designed for this study is capable of operating at Z 1 (100-150 mm), Z 2 (140-210 mm) and Z 3 (170-250 mm) vehicle assembly ground clearance range classes with a very compact vehicle-side (secondary) coupler. The couplers are characterized for the maximum output power (P out ) and the coupling coefficient (k) with different airgaps. System frequency response and the sensitivity analysis are presented. Experimental results are shown for 190.5 mm and 216 mm airgap separations. These results demonstrate that the proposed system with a very compact secondary can be operated at these ground clearance classes with high efficiency at WPT level-3 charging levels.
Onar, Omer↗
A Simple Control to Reduce Device Over-Voltage Caused by Non-Active Switch Loop in Three-Level ANPC Converters
With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices increases, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage caused by additional non-active switch loop can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the device over-voltage. The nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing additional hardware circuit or complex software algorithm is proposed to attenuate the effect of the nonlinear output capacitance. Multi-pulse test is conducted for a 3L-ANPC converter built with silicon carbide (SiC) MOSFETs. With the proposed control, the testing results show that the peak drain-source voltage of both active and non-active switches is reduced by more than 20% compared to the conventional control.
Gui, Handong↗
Current Source Gate Drive to Reduce Switching Loss for SiC MOSFETs
With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.
Gui, Handong↗
Investigation of Fourth-leg for Common-mode Noise Reduction in Three-level Neutral Point Clamped Inverter Fed Motor Drive
The four-leg topology has been applied to two-level inverters for common-mode (CM) noise elimination. To achieve zero common-mode voltage (CMV), the zero vector typically used in the two-level inverter is not allowed. As a result, the reference cannot be synthesized by nearest three vectors, which introduces a penalty in dc voltage utilization and current THD. This paper applies the fourth-leg to three-level neutral point clamped (NPC) inverter fed motor drives. Unlike the case in the two-level inverter, the reference can be synthesized by the nearest three vectors while zero CMV can be achieved at the same time in a three-level inverter with the fourth-leg. The topology and modulation are presented. The fourth-leg filter structures are investigated, and a fourth-leg filter structure which decouples the fourth-leg from the main circuit power level is proposed for high power applications. The experiment results on a three-level NPC inverter show that with the fourth-leg and presented modulation applied, the CM noise has been significantly reduced, and around 25 dB attenuation can be observed at the first noise peak in the electromagnetic interference (EMI) frequency range.
Chen, Ruirui↗