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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,189 records · Page 66
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Anomalous elastic softening in ferroelectric hafnia under pressure

his study employs first-principles density-functional theory (DFT) calculations to explore the elastic and mechanical properties of ferroelectric hafnia (HfO 2 ) in its polar orthorhombic 𝑃⁢𝑐⁢𝑎⁢2 1 phase under varying hydrostatic pressure conditions up to 30 GPa. Utilizing a plane-wave basis set and Perdew-Burke-Ernzerhof generalized-gradient approximation for solids in our DFT calculations, we investigate both pure and yttrium-substituted HfO 2 . Our findings reveal an anomalous reduction in the 𝐶 33 component of the elastic tensor with increasing pressure, which becomes significant above 15 GPa and signals a potential pressure-driven structural phase transition at higher pressure. The analysis of atomic displacements under pressure sheds light on the unusual mechanical behavior and phase stability of this material. Additionally, we observe a transition from an indirect band gap to a direct band gap with increasing pressure, which could have significant implications for optical applications. Here, the effects of yttrium substitution on the mechanical and electronic properties are further examined, revealing that yttrium substitution softens the elastic response of this material and reduces the electronic band gap. These results enhance our understanding of elastic and mechanical responses of ferroelectric hafnia and its potential for applications in microelectronics, piezoelectric devices, and nonvolatile ferroelectric random-access memories. Further experimental validation is recommended to confirm our predictions and explore the practical implications of the observed phase transitions and electronic behavior of the ferroelectric hafnia under high-pressure conditions.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Preparation of excited states for nuclear dynamics on a quantum computer

We study two different methods to prepare excited states on a quantum computer, a key initial step to study dynamics within linear response theory. The first method uses unitary evolution for a short time T = O(√1 - F) to approximate the action of an excitation operator Ô with fidelity F and success probability P ≈ 1 – F. The second method probabilistically applies the excitation operator using the Linear Combination of Unitaries (LCU) algorithm. We benchmark these techniques on emulated and real quantum devices, using a toy model for thermal neutron-proton capture. Despite its larger memory footprint, the LCU-based method is efficient even on current generation noisy devices and can be implemented at a lower gate cost than a naive analysis would suggest. Here, these findings show that quantum techniques designed to achieve good asymptotic scaling on fault tolerant quantum devices might also provide practical benefits on devices with limited connectivity and gate fidelity.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2022

Synthesis and electrical behavior of VO 2 thin films grown on SrRuO 3 electrode layers

VO 2 thin films were grown on conducting oxide underlayer SrRuO 3 buffered SrTiO 3 (111) and Si/SiO 2 substrates, respectively, using sputtering. X-ray diffraction phi-scans revealed the epitaxial nature of the VO 2 films grown on SrRuO 3 buffered SrTiO 3 and polycrystalline structure for films grown on SrRuO 3 buffered Si/SiO 2 . X-ray photoelectron spectroscopy confirms a dominant presence of V 4+ in both films and establishes a high-quality growth of single-phase VO 2 films. Temperature and electric-field driven metal-insulator-transition in both the in-plane and out-of-plane configurations were investigated. Depending on the configuration, the resistance change across the metal-insulator-transition varies from a factor of 1.57–3. The measured resistance in each state as well as the magnitude of resistance change were similar during temperature and electric-field driven metal-insulator-transition. To shed light on the suppressed metal-insulator-transition characteristics due to the current shunting effect from conducting SrRuO 3 bottom electrode, a distributed resistance network model is proposed and benchmarked against reports from the literature. Here, the results demonstrate the growth of high-quality VO 2 on conducting SrRuO 3 layers and their electrical behavior, which is of particular interest for all-oxide electronic devices utilizing phase transitions such as resistive memory and neuromorphic oscillators.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Timely Reporting of Heavy Hitters Using External Memory

Given an input stream S of size N, a Φ-heavy hitter is an item that occurs at least ΦN times in S. The problem of finding heavy-hitters is extensively studied in the database literature. In this work, we study a real-time heavy-hitters variant in which an element must be reported shortly after we see its T = Φ N-th occurrence (and hence it becomes a heavy hitter). We call this the Timely Event Detection (TED) Problem. The TED problem models the needs of many real-world monitoring systems, which demand accurate (i.e., no false negatives) and timely reporting of all events from large, high-speed streams with a low reporting threshold (high sensitivity). Like the classic heavy-hitters problem, solving the TED problem without false-positives requires large space (Ω (N) words). Thus in-RAM heavy-hitters algorithms typically sacrifice accuracy (i.e., allow false positives), sensitivity, or timeliness (i.e., use multiple passes). We show how to adapt heavy-hitters algorithms to external memory to solve the TED problem on large high-speed streams while guaranteeing accuracy, sensitivity, and timeliness. Our data structures are limited only by I/O-bandwidth (not latency) and support a tunable tradeoff between reporting delay and I/O overhead. With a small bounded reporting delay, our algorithms incur only a logarithmic I/O overhead. We implement and validate our data structures empirically using the Firehose streaming benchmark. Multi-threaded versions of our structures can scale to process 11M observations per second before becoming CPU bound. In comparison, a naive adaptation of the standard heavy-hitters algorithm to external memory would be limited by the storage device’s random I/O throughput, i.e., ≈100K observations per second.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1976

TSE computers - A means for massively parallel computations

A description is presented of hardware concepts for building a massively parallel processing system for two-dimensional data. The processing system is to use logic arrays of 128 x 128 elements which perform over 16 thousand operations simultaneously. Attention is given to image data, logic arrays, basic image logic functions, a prototype negator, an interleaver device, image logic circuits, and an image memory circuit.

Strong, J. P., III↗
NASA NTRS1979

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

Klute, A.↗
NASA NTRS1986

Function Generator for Image Processor

Basic elements of function generator are memory chips and interpolator chip, which incorporates multipliers and adders. Memory includes CMOS static random-access devices. 120 ns cycle time of devices allows real-time processing of image data.

Gennery, D. B.↗
NASA NTRS1992

Laser Scanner Tests For Single-Event Upsets

Microelectronic advanced laser scanner (MEALS) is opto/electro/mechanical apparatus for nondestructive testing of integrated memory circuits, logic circuits, and other microelectronic devices. Multipurpose diagnostic system used to determine ultrafast time response, leakage, latchup, and electrical overstress. Used to simulate some of effects of heavy ions accelerated to high energies to determine susceptibility of digital device to single-event upsets.

Kim, Quiesup↗
NASA NTRS1992

Joint Japan/U.S. Conference on Adaptive Structures, 2nd, Nagoya, Japan, Nov. 12-14, 1991, Collection of Papers

The present conference discusses the development status of adaptive structures in Europe and in Japan, the 'Cosmo-Lab' structures/robotics cooperation concept, active-adhesion concepts for in-orbit structural assembly, adaptively controlled truss structures, object-oriented modeling in structural analysis, the control effectiveness and energy efficiency of an active mass damper, a space truss with experimental tendon control, and piezoelectric actuator-based space trusses. Also discussed is the control of resonant frequencies in adaptive structures through prestressing, active control of vortex-excited vibrations of flexible cylindrical structures, shape adjustment of a flexible space antenna reflector, the SDIO Adaptive Structures Program, optimal trajectories of iterative manipulation for space robots, a docking device as an adaptive structure, shape-memory polymers and their hybrid composites, and fuzzy control methods for structural dynamics.

Matsuzaki, Yuji↗
NASA NTRS1993

High-speed joint-transform optical image correlator using GaAs/AlGaAs semi-insulating multiple quantum wells and diode lasers

We demonstrate a compact real-time optical image correlator using diode lasers and a semi-insulating GaAs/AlGaAs multiple-quantum-well (SI-MQW) device as the holographic element. With only 3 mW of power incident upon the SI-MQW device, the correlation is obtained in 1 microsec and can be erased in as fast as 2 microsec, which presents the possibility of a system capable of 3 x 10 exp 5 correlations/s. We also show that images can be stored for a controllable length of time (2-25 microsec), which presents possibilities for the use of the SI-MQW device as a data or image buffer memory.

Partovi, A.↗
NASA NTRS1996

The Single Event Effect Characteristics of the 486-DX4 Microprocessor

This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of the on-chip cache, as well as proving that one vendor is superior to the other in terms of latchup susceptibility. Results from this testing were also used to provide a mean-time-between-failure estimate of the 486-DX4 operating in the radiation environment for the International Space Station.

Kouba, Coy↗
NASA NTRS2009

Compact, Low-Overhead, MIL-STD-1553B Controller

A compact and flexible controller has been developed to provide MIL-STD- 1553B Remote Terminal (RT) communications and supporting and related functions with minimal demand on the resources of the system in which the controller is to be installed. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD-1553B is commonly used in defense and space applications.) Many other MIL-STD-1553B RT controllers are complicated, and to enable them to function, it is necessary to provide software and to use such ancillary separate hardware devices as microprocessors and dual-port memories. The present controller functions without need for software and any ancillary hardware. In addition, it contains a flexible system interface and extensive support hardware while including on-chip error-checking and diagnostic support circuitry. This controller is implemented within part of a modern field-programmable gate array.

Katz, Richard↗
NASA NTRS2011

High-Temperature Smart Structures for Engine Noise Reduction and Performance Enhancement

One of key NASA goals is to develop and integrate noise reduction technology to enable unrestricted air transportation service to all communities. One of the technical priorities of this activity has been to account for and reduce noise via propulsion/airframe interactions, identifying advanced concepts to be integrated with the airframe to mitigate these noise-producing mechanisms. An adaptive geometry chevron using embedded smart structures technology offers the possibility of maximizing engine performance while retaining and possibly enhancing the favorable noise characteristics of current designs. New high-temperature shape memory alloy (HTSMA) materials technology enables the devices to operate in both low-temperature (fan) and high-temperature (core) exhaust flows. Chevron-equipped engines have demonstrated reduced noise in testing and operational use. It is desirable to have the noise benefits of chevrons in takeoff/landing conditions, but have them deployed into a minimum drag position for cruise flight. The central feature of the innovation was building on rapidly maturing HTSMA technology to implement a next-generation aircraft noise mitigation system centered on adaptive chevron flow control surfaces. In general, SMA-actuated devices have the potential to enhance the demonstrated noise reduction effectiveness of chevron systems while eliminating the associated performance penalty. The use of structurally integrated smart devices will minimize the mechanical and subsystem complexity of this implementation. The central innovations of the effort entail the modification of prior chevron designs to include a small cut that relaxes structural stiffness without compromising the desired flow characteristics over the surface; the reorientation of SMA actuation devices to apply forces to deflect the chevron tip, exploiting this relaxed stiffness; and the use of high-temperature SMA (HTSMA) materials to enable operation in the demanding core chevron environment. The overall conclusion of these design studies was that the cut chevron concept is a critical enabling step in bringing the variable geometry core chevron within reach. The presence of the cut may be aerodynamically undesirable in some respects, but it is present only when the chevron is not immersed in the core jet exhaust. When deployed, the gap closes as the chevron tip enters the high-speed, high-temperature core stream. Aeroacoustic testing and flow visualization support the contention that this cut is inconsequential to chevron performance.

Quackenbush, Todd R.↗
DOE OSTI2012

Rational Design of Molecular Ferroelectric Materials and Nanostructures

The purpose of this project was to gain insight into the properties of molecular ferroelectrics through the detailed study of oligomer analogs of polyvinylidene fluoride (PVDF). By focusing on interactions at both the molecular level and the nanoscale level, we expect to gain improved understanding about the fundamental mechanism of ferroelectricity and its key properties. The research consisted of three complementary components: 1) Rational synthesis of VDF oligomers by Prof. Takacs' group; 2) Detailed structural and electrical studies of thin by Prof. Ducharme's Group; and 3) First-principles computational studies by DOE Lab Partner Dr. Serge Nakhmanson at Argonne National Laboratory. The main results of the work was a detailed understanding of the relationships between the molecular interactions and macroscopic phenomenology of ferroelectricity VDF oligomers. This is valuable information supporting the development of improved electromechanical materials for, e.g., sonar, ultrasonic imaging, artificial muscles, and compliant actuators. Other potential applications include nonvolatile ferroelectric memories, heat-sensing imaging arrays, photovoltaic devices, and functional biomimetic materials. The project contributed to the training and professional development of undergraduate students and graduate students, post-doctoral assistants, and a high-school teacher. Project personnel took part in several outreach and education activities each year.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Method and apparatus for reordering in a non-uniform compute device

A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.

97 MATHEMATICS AND COMPUTING↗