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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,189 records · Page 66

All sources NASA NTRS DOE OSTI

NASA NTRS2018

Using GPS Receiver 1PPS Output to Verify Time Stamp Accuracy and Measure Propagation Delay

A simple pulse overlay circuit using a logic OR gate was developed to overlay a precise leading edge 1 pulse per second time reference marker from a global positioning system receiver onto a non-return -to- zero-level pulse code modulation telemetry data stream to validate time stamp accuracy and measure propagation delay in telemetry equipment. A pulse overlay (PO) circuit was designed to produce a time reference marker within a pulse code modulation (PCM) telemetry data stream that was recorded and analyzed to validate an IRIG Standard 106-17 Chapter 10 recorder’s time stamp accuracy [1]. A manufacturer of a newly purchased Chapter 10 recorder claimed the time stamp accuracy to be better than 10 microseconds (μs) with only IRIG-B120 (IRIG-B) input and better than 1 μs with IRIG-B and one pulse per second (1PPS) inputs. The PO circuit and a Chapter 10 recorder test setup were used to verify the vendor’s data-time synchronization claims and to justify infrastructure upgrade costs to connect additional cables to each purchased recorder. The circuit was also used to measure the propagation delay (PD) of a long distance Telemetry multiplexer/demultiplexer telecommunication system which the manufacturer did not provide a PD specification. Using the one pulse per second time reference marker of the global positioning system receiver and the pulse overlay circuit to overlay the one pulse per second variable pulse width signal into a pulse code modulation telemetry stream provided an excellent means to validate time stamp accuracy within a Chapter 10 recorder and to measure propagation delays within a normal telemetry operating environment. The positive results from the Chapter 10 recorder tests validated the vendor’s claims and justified the implementation to add the one pulse per second signal to the range Chapter 10 recorders. The pulse overlay circuit and test setups defined in this paper can easily be used to measure other telemetry equipment.

Knudtson, Kevin↗

NASA NTRS2013

Trade Space Specification Tool (TSST) for Rapid Mission Architecture (Version 1.2)

Trade Space Specification Tool (TSST) is designed to capture quickly ideas in the early spacecraft and mission architecture design and categorize them into trade space dimensions and options for later analysis. It is implemented as an Eclipse RCP Application, which can be run as a standalone program. Users rapidly create concept items with single clicks on a graphical canvas, and can organize and create linkages between the ideas using drag-and-drop actions within the same graphical view. Various views such as a trade view, rules view, and architecture view are provided to help users to visualize the trade space. This software can identify, explore, and assess aspects of the mission trade space, as well as capture and organize linkages/dependencies between trade space components. The tool supports a user-in-the-loop preliminary logical examination and filtering of trade space options to help identify which paths in the trade space are feasible (and preferred) and what analyses need to be done later with executable models. This tool provides multiple user views of the trade space to guide the analyst/team to facilitate interpretation and communication of the trade space components and linkages, identify gaps in combining and selecting trade space options, and guide user decision-making for which combinations of architectural options should be pursued for further evaluation. This software provides an environment to capture mission trade space elements rapidly and assist users for their architecture analysis. This is primarily focused on mission and spacecraft architecture design, rather than general-purpose design application. In addition, it provides more flexibility to create concepts and organize the ideas. The software is developed as an Eclipse plug-in and potentially can be integrated with other Eclipse-based tools.

Wang, Yeou-Fang↗

DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗

NASA NTRS1979

Multivariable control altitude demonstration on the F100 turbofan engine

The control system designed under the Multivariable Control Synthesis (MVCS) program for the F100 turbofan engine is described. The MVCS program, applied the linear quadratic regulator (LQR) synthesis methods in the design of a multivariable engine control system to obtain enhanced performance from cross-coupled controls, maximum use of engine variable geometry, and a systematic design procedure that can be applied efficiently to new engine systems. Basic components of the control system, a reference value generator for deriving a desired equilibrium state and an approximate control vector, a transition model to produce compatible reference point trajectories during gross transients, gain schedules for producing feedback terms appropriate to the flight condition, and integral switching logic to produce acceptable steady-state performance without engine operating limit exceedance are described and the details of the F100 implementation presented. The engine altitude test phase of the MVCS program, and engine responses in a variety of test operating points and power transitions are presented.

Lehtinen, B.↗

NASA NTRS1986

Flight testing TECS - The Total Energy Control System

This paper describes some of the unique features of an integrated throttle-elevator control law known as the Total Energy Control System (TECS) which has been flight tested on NASA Langley's Transport Systems Research Vehicle. The TECS concept is designed around total energy principles. It utilizes a full-time autothrottle to control the total energy of the aircraft and the elevator to distribute the energy between speed and flight path objectives. Time histories of selected parameters generated from flight data are used to illustrate the pilot-like control strategy of the system and the priority logic employed when throttle limiting is encountered.

Kelly, James R.↗

NASA NTRS1998

A Formal Model of Partitioning for Integrated Modular Avionics

The aviation industry is gradually moving toward the use of integrated modular avionics (IMA) for civilian transport aircraft. An important concern for IMA is ensuring that applications are safely partitioned so they cannot interfere with one another. We have investigated the problem of ensuring safe partitioning and logical non-interference among separate applications running on a shared Avionics Computer Resource (ACR). This research was performed in the context of ongoing standardization efforts, in particular, the work of RTCA committee SC-182, and the recently completed ARINC 653 application executive (APEX) interface standard. We have developed a formal model of partitioning suitable for evaluating the design of an ACR. The model draws from the mathematical modeling techniques developed by the computer security community. This report presents a formulation of partitioning requirements expressed first using conventional mathematical notation, then formalized using the language of SRI'S Prototype Verification System (PVS). The approach is demonstrated on three candidate designs, each an abstraction of features found in real systems.

DiVito, Ben L.↗

NASA NTRS2003

Tracking and Control of Gas Turbine Engine Component Damage/Life

This paper describes damage mechanisms and the methods of controlling damages to extend the on-wing life of critical gas turbine engine components. Particularly, two types of damage mechanisms are discussed: creep/rupture and thermo-mechanical fatigue. To control these damages and extend the life of engine hot-section components, we have investigated two methodologies to be implemented as additional control logic for the on-board electronic control unit. This new logic, the life-extending control (LEC), interacts with the engine control and monitoring unit and modifies the fuel flow to reduce component damages in a flight mission. The LEC methodologies were demonstrated in a real-time, hardware-in-the-loop simulation. The results show that LEC is not only a new paradigm for engine control design, but also a promising technology for extending the service life of engine components, hence reducing the life cycle cost of the engine.

Jaw, Link C.↗

NASA NTRS2013

Programmable Ultra Lightweight System Adaptable Radio (PULSAR) Low Cost Telemetry - Access from Space Advanced Technologies or Down the Middle

Software Defined Radio (SDR) technology has been proven in the commercial sector since the early 1990's. Today's rapid advancement in mobile telephone reliability and power management capabilities exemplifies the effectiveness of the SDR technology for the modern communications market. In contrast, presently qualified satellite transponder applications were developed during the early 1960's space program. Programmable Ultra Lightweight System Adaptable Radio (PULSAR, NASA-MSFC SDR) technology revolutionizes satellite transponder technology by increasing data through-put capability by, at least, an order of magnitude. PULSAR leverages existing Marshall Space Flight Center SDR designs and commercially enhanced capabilities to provide a path to a radiation tolerant SDR transponder. These innovations will (1) reduce the cost of NASA Low Earth Orbit (LEO) and Deep Space transponders, (2) decrease power requirements, and (3) a commensurate volume reduction. Also, PULSAR increases flexibility to implement multiple transponder types by utilizing the same hardware with altered logic - no analog hardware change is required - all of which can be accomplished in orbit. This provides high capability, low cost, transponders to programs of all sizes. The final project outcome would be the introduction of a Technology Readiness Level (TRL) 7 low-cost CubeSat to SmallSat telemetry system into the NASA Portfolio.

Sims. Herb↗

NASA NTRS2009

Universal Reconfigurable Translator Module (URTM) Final Report

This report describes the Universal Reconfigurable Translation Module, or URTM. The URTM was developed by Sigma Space Corporation for NASA in order to translate specific serial protocols, both logically and physically. At present, the prototype configuration has targeted MIL-STD-1553B (RT and BC), IEEE 1394b (Firewire), and ECSS-E-50-12A (SpaceWire). The objectives of this program were to study the feasibility of a configurable URTM to translate serial link data as might be used in a space-flight mission and to design, develop, document, and deliver an engineering prototype model of the URTM with a path to spaceflight. By simply connecting two of the three Physical Interface Modules (PIM) on either end of the RPTM (Reconfigurable Protocol Translator Module), the URTM then self configures via a library of interface translation functions, thereby allowing the two data links to communicate seamlessly.

Leventhal, Edward↗

NASA NTRS2020

Event-Driven Modeling and Execution of Robotic Activities and Contingencies in the Europa Lander Mission Concept Using BPMN

TRACE (Traceable Robotic Activity Composer and Executive) is a tool designed to address the model-ing, verification, and execution of planned and con-tingent activities during robotic space missions. These activities can be modeled (i.e., planned) graph-ically in TRACE using the Business Process Model and Notation (BPMN) language. This standardized language is used to model a sequence of robotic ac-tivities tied together by logical constructs, events, and time. TRACE includes verification tools to en-sure feasibility before mission models are executed by TRACE’s executive, which is integrated into the autonomy subsystem via a connector. In this paper, we describe TRACE in detail as it would apply to a conceptual Europa Lander surface mission with planned excavation and sample collection activities, as well as, contingency activities when execution is off-nominal—all highlighting our novel use of BPMN as a lingua franca for the pipeline from mis-sion planning to autonomous execution.

Lim, Grace↗

NASA NTRS2011

Evaluation of an Airborne Spacing Concept, On-Board Spacing Tool, and Pilot Interface

The number of commercial aircraft operations is predicted to increase in the next ten years, creating a need for improved operational efficiency. Two areas believed to offer significant increases in efficiency are optimized profile descents and dependent parallel runway operations. It is envisioned that during both of these types of operations, flight crews will precisely space their aircraft behind preceding aircraft at air traffic control assigned intervals to increase runway throughput and maximize the use of existing infrastructure. This paper describes a human-in-the-loop experiment designed to study the performance of an onboard spacing algorithm and pilots ratings of the usability and acceptability of an airborne spacing concept that supports dependent parallel arrivals. Pilot participants flew arrivals into the Dallas Fort-Worth terminal environment using one of three different simulators located at the National Aeronautics and Space Administration s (NASA) Langley Research Center. Scenarios were flown using Interval Management with Spacing (IM-S) and Required Time of Arrival (RTA) control methods during conditions of no error, error in the forecast wind, and offset (disturbance) to the arrival flow. Results indicate that pilots delivered their aircraft to the runway threshold within +/- 3.5 seconds of their assigned arrival time and reported that both the IM-S and RTA procedures were associated with low workload levels. In general, pilots found the IM-S concept, procedures, speeds, and interface acceptable; with 92% of pilots rating the procedures as complete and logical, 218 out of 240 responses agreeing that the IM-S speeds were acceptable, and 63% of pilots reporting that the displays were easy to understand and displayed in appropriate locations. The 22 (out of 240) responses, indicating that the commanded speeds were not acceptable and appropriate occurred during scenarios containing wind error and offset error. Concerns cited included the occurrence of multiple speed changes within a short time period, speed changes required within twenty miles of the runway, and an increase in airspeed followed shortly by a decrease in airspeed. Within this paper, appropriate design recommendations are provided, and the need for continued, iterative human-centered design is discussed.

Swieringa, Kurt↗

NASA NTRS2005

Multifunctional Logic Gate Controlled by Supply Voltage

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Stoica, Adrian↗

DOE OSTI2024

Accelerating polyketide synthase engineering for high TRY production of biofuels and bioproducts (Final Technical Report)

Polyketide synthase (PKS) enzymes have a modular, deterministic logic that holds the potential to act as a flexible chemical factory for the biological production of a huge diversity of valuable small molecule compounds. However, engineering a custom PKS to produce a specific desired product currently requires years of trial and error, for reasons that remain poorly understood. In this project, we have developed a rapid, high throughput, Design-Build-Test-Learn (DBTL) cycle for polyketide synthases (PKSs) and demonstrate its utility for production of materials precursors. The objectives are 1) to develop a rapid, high-throughput (HT) DBTL cycle for PKSs that will enable production of a large number of unnatural, organic molecules on demand at high titer, rate, and yield (TRY); 2) to demonstrate the utility of the PKS DBTL cycle to produce three molecules: one commodity chemical (caprolactam or valerolactam) and two novel materials precursors (caprolactam or valerolactam derivatives); and 3) to demonstrate the utility of the PKS DBTL cycle to increase the TRY of one molecule (caprolactam or valerolactam). In this project, we have successfully demonstrated our high throughput PKS DBTL pipeline, and have biologically produced valerolactam and several other novel nylon monomers.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2023

Accelerating polyketide synthase engineering for high TRY production of biofuels and bioproducts (CRADA Final Report)

09 BIOMASS FUELS↗

DOE OSTI2026

PVDeg: Enhancing Usability and AI-Driven Multi-Mechanism Degradation Modeling

PVDeg version 0.7.0, released in December 2025, introduced major enhancements to improve usability and performance. This update reorganized tutorials and tool notebooks to create a more intuitive experience, enabling users to easily follow and adapt workflows for their specific analyses. In addition to structural improvements, both the notebooks and core logic underwent significant optimization for efficiency, robustness, and style. These refinements were supported by new testing frameworks built on nbval and pytest, adherence to PEP8 standards, and extensive code refactoring, which collectively simplify onboarding for new developers. Looking ahead, version 0.8.0 will deliver advanced AI-driven capabilities. The primary focus is to further develop and automate the degradation workflow, designed to analyze PV module degradation across diverse locations and system configurations. By integrating large language models (LLMs) to scan literature and compile a comprehensive database of materials and degradation rates, this feature will enable modeling of multiple materials and mechanisms within a single, streamlined workflow. Users will be able to evaluate degradation impacts on different system architectures under varying environmental conditions, facilitating informed decisions on bill-of-materials optimization for specific deployment scenarios. These advancements position PVDeg as a powerful, user-friendly tool for accelerating PV reliability research and system design.

14 SOLAR ENERGY↗

NASA NTRS1976

Some effects of adverse weather conditions on performance of airplane antiskid braking systems

The performance of current antiskid braking systems operating under adverse weather conditions was analyzed in an effort to both identify the causes of locked-wheel skids which sometimes occur when the runway is slippery and to find possible solutions to this operational problem. This analysis was made possible by the quantitative test data provided by recently completed landing research programs using fully instrumented flight test airplanes and was further supported by tests performed at the Langley aircraft landing loads and traction facility. The antiskid system logic for brake control and for both touchdown and locked-wheel protection is described and its response behavior in adverse weather is discussed in detail with the aid of available data. The analysis indicates that the operational performance of the antiskid logic circuits is highly dependent upon wheel spin-up acceleration and can be adversely affected by certain pilot braking inputs when accelerations are low. Normal antiskid performance is assured if the tire-to-runway traction is sufficient to provide high wheel spin-up accelerations or if the system is provided a continuous, accurate ground speed reference. The design of antiskid systems is complicated by the necessity for tradeoffs between tire braking and cornering capabilities, both of which are necessary to provide safe operations in the presence of cross winds, particularly under slippery runway conditions.

Horne, W. B.↗

NASA NTRS1994

VLSI neuroprocessors

Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional techniques and enables multiple assignments, (many to many), not achievable with standard statistical approaches. Tactical movement planning (finding the best path from A to B) is accomplished with a digital two-dimensional concurrent processor array. By exploiting the natural parallel decomposition of the problem in silicon, a four order of magnitude speed-up over optimized software approaches has been demonstrated.

Kemeny, Sabrina E.↗

NASA NTRS1995

PSC implementation and integration

Hardware and software design of the performance seeking control (PSC) for the NASA F-15 research aircraft are described. The hardware architecture, vehicle management system computer (VMSC), pilot interface, and PSC mode selection are discussed. The PSC software is distributed among the VMSC, central computer, digital electronic engine controls (DEEC's), and electronic air inlet controllers (EAIC's). The major PSC modules, VMSC logic, VMSC channel C memory requirements, VMSC channel C timing, and navigation control indicator (NCI) variables and where they are located are presented.

Nobbs, Steven↗