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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,171 records · Page 65
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Integrating Efficiency of Industry Processes and Practices Alongside Technology Effectiveness in Space Transportation Cost Modeling and Analysis

This paper presents past and current work in dealing with indirect industry and NASA costs when providing cost estimation or analysis for NASA projects and programs. Indirect costs, when defined as those costs in a project removed from the actual hardware or software hands-on labor; makes up most of the costs of today's complex large scale NASA space/industry projects. This appears to be the case across phases from research into development into production and into the operation of the system. Space transportation is the case of interest here. Modeling and cost estimation as a process rather than a product will be emphasized. Analysis as a series of belief systems in play among decision makers and decision factors will also be emphasized to provide context.

Zapata, Edgar↗
DOE OSTI2023

Hierarchical multi-time-scale predictive thermal management and fuel optimization for heavy-duty compression ignition engines

For heavy-duty diesel engines, NO X emissions reduction is strongly constrained by fuel efficiency. This paper presents a hierarchical model predictive controller (H-MPC) for coordinated control of tailpipe NO X emissions and fuel consumption. The H-MPC uses the separation of slow and fast dynamics that exist in the engine and its aftertreatment system. The controller is synthesized with an architecture in which a high-level MPC uses a longer prediction horizon compared to the low-level predictive controller which tracks the high-level controller command and manages the thermal dynamics of the aftertreatment system. Engine load preview enables the high-level controller to estimate the desired catalyst temperature ahead of time and addresses the selective catalytic reduction (SCR) slow thermal dynamics. Calculated by the high-level controller, the intake manifold pressure, and the start of injection (SOI) crank angle is used as reference trajectories in the low-level controller that regulates fast dynamical behaviors such as engine out NO X emissions. Hardware-in-the-loop (HIL) validation of this integrated H-MPC on a rapid prototype controller shows that when the SCR catalyst temperature is above light-off temperature (warmed-up condition), the engine operation is shifted to operate with the best fuel economy since the warmed-up SCR can efficiently reduce the engine-out NO X emissions. Results indicate that up to 0.8% benefit in cycle averaged BSFC along with a 13% reduction in tailpipe NO X compared to a stock engine calibration can be achieved with the coordinated engine and aftertreatment system through H-MPC.

Engineering↗
DOE OSTI2021

Multichannel Analysis of Surface Waves Accelerated (MASWAccelerated): Software for efficient surface wave inversion using MPI and GPUs

Multichannel Analysis of Surface Waves (MASW) is a technique frequently used in geotechnical engineering and engineering geophysics to infer 1D layered models of seismic shear wave velocities in the top tens to hundreds of meters of the subsurface. We aim to accelerate MASW calculations by capitalizing on modern computer hardware available in the workstations of most engineers: multiple cores and graphics processing units (GPUs). We propose new parallel and GPU accelerated algorithms for computing 1D MASW inversion, and provide software implementations in C using Message Passing Interface (MPI) and CUDA. These algorithms take advantage of sparsity that arises in the problem, and the work balance between processes considers typical data trends. We compare our methods to an existing open source Matlab MASW tool. Our serial C implementation achieves a 2x speedup over the Matlab software, and we continue to see improvements by parallelizing the problem with MPI. Here we see nearly perfect strong and weak scaling for uniform data, and improve strong scaling for realistic data by repartitioning the problem to process mapping. By utilizing GPUs available on most modern workstations, we observe an additional 1.3x speedup over the serial C implementation on the first use of the method. We typically repeatedly evaluate theoretical dispersion curves as part of an optimization procedure, and on the GPU the kernel can be cached for faster reuse on later runs. We observe a 3.2x speedup on the cached GPU runs compared to the serial C runs. This work is the first open-source parallel or GPU-accelerated software tool for MASW imaging, and should enable geotechnical engineers to fully utilize all computer hardware at their disposal.

58 GEOSCIENCES↗
DOE OSTI2022

A Length Adaptive Algorithm-Hardware Co-design of Transformer on FPGA Through Sparse Attention and Dynamic Pipelining

Transformers are considered one of the most important deep learning models since 2018, in part because it establishes state-of-the-art (SOTA) records and could potentially replace existing Deep Neural Networks (DNNs). Despite the remarkable triumphs, the prolonged turnaround time of Transformer models is a widely recognized roadblock. The variety of sequence lengths imposes additional computing overhead where inputs need to be zero-padded to the maximum sentence length in the batch to accommodate the parallel computing platforms. This paper targets the field-programmable gate array (FPGA) and proposes a coherent sequence length adaptive algorithm–hardware co-design for Transformer acceleration. Particularly, we develop a hardware-friendly sparse attention operator and a length-aware hardware resource scheduling algorithm. The proposed sparse attention operator brings the complexity of attention-based models down to linear complexity and alleviates the off-chip memory traffic. The proposed length-aware resource hardware scheduling algorithm dynamically allocates the hardware resources to fill up the pipeline slots and eliminates bubbles for NLP tasks. Experiments show that our design has very small accuracy loss and has 80.2 × and 2.6 × speedup compared to CPU and GPU implementation, and 4 × higher energy efficiency than state-of-the-art GPU accelerator optimized via CUBLAS GEMM.

Peng, Hongwu↗
DOE OSTI2023

Studying light–matter interactions and energy transfer at the nanoscale with a trapped–ion quantum computer

A grand challenge in materials sciences is to control energy transduction, transfer and dissipation at the nanoscale. Meeting this challenge requires progress in nanoscale fabrication and synthesis, but equally importantly, also progress in our understanding of how nanoscale structure influences these phenomena. Although detailed quantum mechanical models exist that capture the structure and physics of materials and molecular species, solving these models to calculate the relevant emergent phenomena, which often occur over vastly different time and energy scales, has so far proven difficult. In this project, we studied how to model energy transfer and light-matter interactions using trapped-ion quantum computers. Our studies focused on emulation of critical processes in natural systems, such as the well-known photosynthetic pigment-protein complexes responsible for capturing and transducing light to electrons. In addition, we implemented proof-of-principle experiments demonstrating that such calculations are possible on trapped-ion quantum computing hardware. These studies and experiments pave the way to investigate energy transport and transduction in a detail not accessible with classical computing technologies. We expect that our studies will allow to extract important guiding principles on how to improve the efficiency of nano-scale light-harvesting and transduction devices.

36 MATERIALS SCIENCE↗
NASA NTRS1982

An emulator for minimizing finite element analysis implementation resources

A finite element analysis emulator providing a basis for efficiently establishing an optimum computer implementation strategy when many calculations are involved is described. The SCOPE emulator determines computer resources required as a function of the structural model, structural load-deflection equation characteristics, the storage allocation plan, and computer hardware capabilities. Thereby, it provides data for trading analysis implementation options to arrive at a best strategy. The models contained in SCOPE lead to micro-operation computer counts of each finite element operation as well as overall computer resource cost estimates. Application of SCOPE to the Memphis-Arkansas bridge analysis provides measures of the accuracy of resource assessments. Data indicate that predictions are within 17.3 percent for calculation times and within 3.2 percent for peripheral storage resources for the ELAS code.

Melosh, R. J.↗
NASA NTRS1991

Process and assembly plans for low cost commercial fuselage structure

Cost and weight reduction for a composite structure is a result of selecting design concepts that can be built using efficient low cost manufacturing and assembly processes. Since design and manufacturing are inherently cost dependent, concurrent engineering in the form of a Design-Build Team (DBT) is essential for low cost designs. Detailed cost analysis from DBT designs and hardware verification must be performed to identify the cost drivers and relationships between design and manufacturing processes. Results from the global evaluation are used to quantitatively rank design, identify cost centers for higher ranking design concepts, define and prioritize a list of technical/economic issues and barriers, and identify parameters that control concept response. These results are then used for final design optimization.

Willden, Kurtis↗
NASA NTRS1993

Solar dynamic power system development for Space Station Freedom

The development of a solar dynamic electric power generation system as part of the Space Station Freedom Program is documented. The solar dynamic power system includes a solar concentrator, which collects sunlight; a receiver, which accepts and stores the concentrated solar energy and transfers this energy to a gas; a Brayton turbine, alternator, and compressor unit, which generates electric power; and a radiator, which rejects waste heat. Solar dynamic systems have greater efficiency and lower maintenance costs than photovoltaic systems and are being considered for future growth of Space Station Freedom. Solar dynamic development managed by the NASA Lewis Research Center from 1986 to Feb. 1991 is covered. It summarizes technology and hardware development, describes 'lessons learned', and, through an extensive bibliography, serves as a source list of documents that provide details of the design and analytic results achieved. It was prepared by the staff of the Solar Dynamic Power System Branch at the NASA Lewis Research Center in Cleveland, Ohio. The report includes results from the prime contractor as well as from in-house efforts, university grants, and other contracts. Also included are the writers' opinions on the best way to proceed technically and programmatically with solar dynamic efforts in the future, on the basis of their experiences in this program.

Source record↗
NASA NTRS1991

VHDL simulation with access to transistor models

Hardware description languages such as VHDL have evolved to aid in the design of systems with large numbers of elements and a wide range of electronic and logical abstractions. For high performance circuits, behavioral models may not be able to efficiently include enough detail to give designers confidence in a simulation's accuracy. One option is to provide a link between the VHDL environment and a transistor level simulation environment. The coupling of the Vantage Analysis Systems VHDL simulator and the NOVA simulator provides the combination of VHDL modeling and transistor modeling.

Gibson, J.↗
NASA NTRS1995

The scheme machine: A case study in progress in design derivation at system levels

The Scheme Machine is one of several design projects of the Digital Design Derivation group at Indiana University. It differs from the other projects in its focus on issues of system design and its connection to surrounding research in programming language semantics, compiler construction, and programming methodology underway at Indiana and elsewhere. The genesis of the project dates to the early 1980's, when digital design derivation research branched from the surrounding research effort in programming languages. Both branches have continued to develop in parallel, with this particular project serving as a bridge. However, by 1990 there remained little real interaction between the branches and recently we have undertaken to reintegrate them. On the software side, researchers have refined a mathematically rigorous (but not mechanized) treatment starting with the fully abstract semantic definition of Scheme and resulting in an efficient implementation consisting of a compiler and virtual machine model, the latter typically realized with a general purpose microprocessor. The derivation includes a number of sophisticated factorizations and representations and is also deep example of the underlying engineering methodology. The hardware research has created a mechanized algebra supporting the tedious and massive transformations often seen at lower levels of design. This work has progressed to the point that large scale devices, such as processors, can be derived from first-order finite state machine specifications. This is roughly where the language oriented research stops; thus, together, the two efforts establish a thread from the highest levels of abstract specification to detailed digital implementation. The Scheme Machine project challenges hardware derivation research in several ways, although the individual components of the system are of a similar scale to those we have worked with before. The machine has a custom dual-ported memory to support garbage collection. It consists of four tightly coupled processes--processor, collector, allocator, memory--with a very non-trivial synchronization relationship. Finally, there are deep issues of representation for the run-time objects of a symbolic processing language. The research centers on verification through integrated formal reasoning systems, but is also involved with modeling and prototyping environments. Since the derivation algebra is basd on an executable modeling language, there is opportunity to incorporate design animation in the design process. We are looking for ways to move smoothly and incrementally from executable specifications into hardware realization. For example, we can run the garbage collector specification, a Scheme program, directly against the physical memory prototype, and similarly, the instruction processor model against the heap implementation.

Johnson, Steven D.↗
NASA NTRSDate not supplied

Astrobee On-Orbit Commissioning

The Astrobee free flying robots operate in the interior of the International Space Station (ISS) under supervisory control of a ground operator or ISS crew. They replace the Synchronized Position Hold Engage and Reorient Experimental Satellites (SPHERES) as research platforms for zero-g free-flying robotics. Astrobee also provides a tool for improving the efficiency of ISS operations as a mobile camera/sensor platform available to flight and payload controllers. The Astrobee system consists of three robots with perching arms, a docking station, and a ground data system. Development began in late-2014, and flight hardware has been deployed to ISS on several launches starting in November 2018 and concluding in October 2019. Shortly after the first two robots arrived on ISS in April, we began a series of "commissioning" activities to validate both space and ground segments. We plan to complete commissioning and become an operational facility available to guest scientists by the end of 2019. This paper provides an overview of the Astrobee system, a description of the on-orbit activities, and commissioning results.

ISS↗
NASA NTRSDate not supplied

Astrobee On-Orbit Commissioning

The Astrobee free flying robots operate in the interior of the International Space Station (ISS) under supervisory control of a ground operator or ISS crew. They replace the Synchronized Position Hold Engage and Reorient Experimental Satellites (SPHERES) as research platforms for zero-g free-flying robotics. Astrobee also provides a tool for improving the efficiency of ISS operations as a mobile camera/sensor platform available to flight and payload controllers. The Astrobee system consists of three robots with perching arms, a docking station, and a ground data system. Development began in late-2014, and flight hardware has been deployed to ISS on several launches starting in November 2018 and concluding in October 2019. Shortly after the first two robots arrived on ISS in April, we began a series of “commissioning” activities to validate both space and ground segments. This paper provides an overview of the Astrobee system, a description of the on-orbit activities, and commissioning results.

Astrobee↗
NASA NTRS2018

Thermal Operability Improvements for the Mars 2020 Rover Surface Mission

The Mars 2020 Rover is scheduled to land on Mars on February 18, 2021. One of the primary mission objectives for the Mars 2020 Rover is to perform in-situ science and collect a set of Martian regolith samples for possible future return to Earth. In order to meet mission requirements, 20 samples must be collected, assessed, and sealed during the prime mission (1.5 Martian years, approximately 1000 Sols). This requires that the Mars 2020 Rover operate in a much more efficient and autonomous manner than its predecessor, the Mars Science Laboratory (MSL) Rover, Curiosity. The thermal designs of both Curiosity and the Mars 2020 Rover utilize warmup heaters to bring the actuators and cameras, located on the outside of the vehicle, up to their operating temperatures prior to use. These heaters consume energy during the mission. The Rover energy balance, between energy production and consumption, must be maintained in order to keep the mission moving safely forward. Increased efficiency in the way this warmup heater energy is allocated and used in the Mars 2020 Rover operations plan will result in more energy available for science and engineering activities. This paper discusses the improvements that were made in both hardware and software to improve the way the Mars 2020 Rover will operate thermally on Mars.

Lee, Chern-Jiin↗
NASA NTRS2022

Qualification and Performance of a High-Efficiency Laser Transmitter for Deep-Space Optical Communications

A high-power Laser Transmitter Assembly (LTA) was developed to support the Deep Space Optical Communications (DSOC) technology demonstration being developed by the Jet Propulsion Laboratory. NASA’s Psyche Mission plans to host the DSOC flight subsystem for testing space-to-ground high-bandwidth laser communications en route to the 16 Psyche asteroid. We review the design, performance, and qualification of the LTA Engineering Model and Flight Model (EM and FM) delivered to JPL. The LTA uses a master-oscillator power amplifier (MOPA) design and delivers up to 4.5 W at 1550 nm, with a highly efficient, cladding-pumped, polarization-maintaining erbium-ytterbium fiber amplifier. The master oscillator generates a range of pulse widths and repetition rates to support modulation formats from 16- to 128-PPM for optical data transmission at >100 Mbps. The LTA was designed for high reliability and radiation hardness, and includes redundant signal and pumping paths to reduce single points of failure, hardware interlocks to ensure safe operation and protection against damage, closed-loop control of optical power, and detailed health and status via telemetry. The LTA EM and FM were subjected to unit-appropriate space qualification testing. We describe the performance testing of the EM and FM, for the characterization of key metrics such as wavelength stability, signal linewidth, optical pulse width, jitter, and extinction ratio, and polarization extinction ratio. The management of optical nonlinearities (self-phase modulation, Brillouin scattering, or pulse-to-pulse energy variation), which could result in an optical link penalty or damage to the LTA, is also detailed, and factors affecting the power efficiency are discussed.

Jaques, J.↗
DOE OSTI2025

Performance Evaluation of Intelligent Solar Control Software Through Hardware-in-the-Loop (CRADA Final Report)

Recent research has highlighted the potential for solar to act as a zero-marginal-cost and zero-emission flexibility resource on the bulk power system when operated with advanced control systems. To increase the performance of these systems, leading technologies, including machine learning (ML) and hierarchical inverter set point allocation, have been developed by Latimer Controls, Inc. to estimate the headroom of large PV plants for grid operation and control; however, these technologies lack comprehensive validation under real-world application scenarios. Latimer Controls, Inc. received two voucher awards for research at a national laboratory from the Department of Energy American Made Solar Prize Round 6. The National Renewable Energy Laboratory (NREL) was selected to collaborate with Latimer staff to conduct a performance evaluation of Latimer PV control software. The NREL team will develop a hardware-in-the-loop (HIL) testbed to perform testing and validation of the Latimer PV control technology in a de-risked yet realistic testbed environment. Latimer and NREL worked together to analyze the test data, draw conclusions from the results, and disseminate the resulting scientific findings. In this CRADA work, we propose to test and validate the real-world application of the Latimer Control solution in an HIL environment. We evaluate the performance of different flexible solar technologies in responding to automatic generation control signals in a closed-loop fashion. In particular, a data-driven potential high limit (PHL) estimation is developed for large solar plants to accurately estimate their headroom so that they have fast and short-time regulation and control capability to participate in grid services and respond to grid signals in real time (e.g., AGC). This PHL estimation algorithm is embedded in a hardware power plant controller (PPC) and tested with an IEEE-39 bus system model developed in RTDS. To account for the varying cloud conditions and diverse inverter dispatches, we developed a 135-MW PV plant with detailed modeling of 27 individual PV modules and inverters using RTDS. The real-world communications used in such big plants, such as ModBus TCP/IP for inverter level and DNP3 for plant level, were developed to emulate the real-world applications in big PV plants. The ML-based PHL estimation method is tested under nine separate weather scenarios against the ‘reference-control’ solution, hereafter referred to as the baseline solution. The baseline method reserves a subset of inverters (reference group) to operate at their PHL at all times and dispatches only the remaining inverters (control group) at curtailed levels to fulfill the flexibility need. Despite being successfully piloted by NREL in California in 2017 and Chile in 2020, there exist two gaps in the state of the art to fully unlock the flexibility of PV plants: a. There is a trade-off between the PHL estimation accuracy and the flexibility range. b. There lacks granularity in the PHL estimation to capture the variation across inverters. The Latimer solution seeks to address these gaps by applying machine learning methods to improve PHL estimation accuracy while accounting for variability at every inverter. Performance metrics were taken from the 2023 Georgia Power CARES utility-scale RFP. The results demonstrate that the ML-based approach outperforms the traditional baseline method in PHL estimation accuracy for 7 of 9 scenarios. The average PHL error across the nine scenarios was 7.40% for the ML-based method, 2.06% less than the 9.46% PHL error average across scenarios that was exhibited by the baseline method. Additionally, the PHL error was below 5% for at least 95% of the testing interval for 3 of 9 tested intervals with the ML approach, whereas it did not achieve this metric for any of the baseline tests. Overall, simulation results indicate the superior performance of an ML-based approach compared to the conventional baseline reference-control approach, showcasing its potential to support grid stability and operational efficiency. This laboratory HIL testing using real PPC, representative power system simulation models in real-time with detailed PV plant and inverter models, and real-world communication protocols gives us confidence that this machine learning based PHL estimation algorithm works well in the hardware PPC and therefore de-risks future field commissioning. The end goal of this project is to advance grid technology to address the grid operation challenges brought by solar plant’s variability and uncertainties in power generation.

14 SOLAR ENERGY↗
DOE OSTI2022

Resilience Design Patterns: A Structured Approach to Resilience at Extreme Scale (V.2.0)

Reliability is a serious concern for future extreme-scale high-performance computing (HPC) systems. Projections based on the current generation of HPC systems and technology roadmaps suggest the prevalence of very high fault rates in future systems. The errors resulting from these faults will propagate and generate various kinds of failures, which may result in outcomes ranging from result corruptions to catastrophic application crashes. Therefore, the resilience challenge for extreme-scale HPC systems requires coordination between various hardware and software technologies that are capable of handling a broad set of fault models at accelerated fault rates. Also, due to practical limits on power consumption in future HPC systems, they are likely to embrace innovative architectures, increasing the levels of hardware and software complexities. Therefore, the techniques that seek to improve resilience must navigate the complex trade-off space between resilience and the overheads to power consumption and performance. While the HPC community has developed various resilience solutions, application-level techniques as well as system-based solutions, the solution space of HPC resilience techniques remains fragmented. There are no formal methods to integrate the various HPC resilience techniques into composite solutions, nor are there methods to holistically evaluate the adequacy and efficacy of such solutions in terms of their protection coverage, and their performance & power efficiency characteristics. Additionally, few implementations of current resilience solutions are portable to newer architectures and software environments that will be deployed on future systems. We developed a new structured approach to the management of HPC resilience using the concept of resilience-based design patterns. In general, a design pattern is a repeatable solution to a commonly occurring problem. We identified the well-known solutions that are commonly used to deal with faults, errors and failures in HPC systems. In the initial design patterns specification (version 1.0), we described the various solutions, which address specific problems in the design of resilient HPC environments, in the form of patterns. Each pattern describes a problem caused by a fault, error or failure event in an HPC environment, and then describes the core of the solution of the problem in such a way that this solution may be adapted to different systems and implemented at different layers of the system stack. The catalog of these resilience design patterns provides designers with a collection of design elements. To construct complete resilience solutions using combinations of various patterns, we defined a framework that enhances HPC designers' understanding of the important constraints and the opportunities for the design patterns to be implemented and deployed at various layers of the system stack. The design framework is also useful for establishing interfaces and mechanisms to coordinate flexible fault management across hardware and software components, as well as to consider the trade-off between performance, resilience, and power consumption when constructing a solution. The resilience design patterns specification version 1.1 included more detailed explanations of the pattern solutions, the context in which the patterns are applicable, and the implications for hardware or software design. It also provided several additional examples and detailed case studies to demonstrate the use of patterns to build realistic solutions. In version 1.2 of the specification document, we have improved the pattern descriptions, including graphical representations of the pattern components. These improvements are largely based on critical comments, feedback and suggestions received from pattern experts and readers of the previous versions of the specification. The pattern classification has been modified to further clarify the relationships between pattern categories. This version of the specification also introduces a pattern language for resilience design patterns. The pattern language presents the patterns in the catalog as a network, revealing the relations among the resilience patterns. The language provides designers with the means to explore alternative techniques for handling a specific fault model that may have different efficiency and complexity characteristics. Using the pattern language also enables the design and implementation of comprehensive resilience solutions as a set of interconnected resilience patterns that can be instantiated across layers of the system stack. The overall goal of this work is to provide hardware and software designers, as well as the users and operators of HPC systems, a systematic methodology for the design and evaluation of resilience technologies in HPC systems that keep scientific applications running to a correct solution in a timely and cost-efficient manner despite frequent faults, errors, and failures of various types. Version 2.0 expands the resilience design pattern classification and catalog to include self-stabilization patterns and reliability, availability and performance models for each structural pattern.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2016

A Multi-Center Space Data System Prototype Based on CCSDS Standards

Deep space missions beyond earth orbit will require new methods of data communications in order to compensate for increasing Radio Frequency (RF) propagation delay. The Consultative Committee for Space Data Systems (CCSDS) standard protocols Spacecraft Monitor & Control (SM&C), Asynchronous Message Service (AMS), and Delay/Disruption Tolerant Networking (DTN) provide such a method. However, the maturity level of this protocol stack is insufficient for mission inclusion at this time. This Space Data System prototype is intended to provide experience which will raise the Technical Readiness Level (TRL) of this protocol set. In order to reduce costs, future missions can take advantage of these standard protocols, which will result in increased interoperability between control centers. This prototype demonstrates these capabilities by implementing a realistic space data system in which telemetry is published to control center applications at the Jet Propulsion Lab (JPL), the Marshall Space Flight Center (MSFC), and the Johnson Space Center (JSC). Reverse publishing paths for commanding from each control center are also implemented. The target vehicle consists of realistic flight computer hardware running Core Flight Software (CFS) in the integrated Power, Avionics, and Power (iPAS) Pathfinder Lab at JSC. This prototype demonstrates a potential upgrade path for future Deep Space Network (DSN) modification, in which the automatic error recovery and communication gap compensation capabilities of DTN would be exploited. In addition, SM&C provides architectural flexibility by allowing new service providers and consumers to be added efficiently anywhere in the network using the common interface provided by SM&C's Message Abstraction Layer (MAL). In FY 2015, this space data system was enhanced by adding telerobotic operations capability provided by the Robot API Delegate (RAPID) family of protocols developed at NASA. RAPID is one of several candidates for consideration and inclusion in a new international standard being developed by the CCSDS Telerobotic Operations Working Group. Software gateways for the purpose of interfacing RAPID messages with the existing SM&C based infrastructure were developed. Telerobotic monitor, control, and bridge applications were written in the RAPID framework, which were then tailored to the NAO telerobotic test article hardware, a product of Aldebaran Robotics.

Rich, Thomas M.↗
NASA NTRS2008

Cell-Detection Technique for Automated Patch Clamping

A unique and customizable machinevision and image-data-processing technique has been developed for use in automated identification of cells that are optimal for patch clamping. [Patch clamping (in which patch electrodes are pressed against cell membranes) is an electrophysiological technique widely applied for the study of ion channels, and of membrane proteins that regulate the flow of ions across the membranes. Patch clamping is used in many biological research fields such as neurobiology, pharmacology, and molecular biology.] While there exist several hardware techniques for automated patch clamping of cells, very few of those techniques incorporate machine vision for locating cells that are ideal subjects for patch clamping. In contrast, the present technique is embodied in a machine-vision algorithm that, in practical application, enables the user to identify good and bad cells for patch clamping in an image captured by a charge-coupled-device (CCD) camera attached to a microscope, within a processing time of one second. Hence, the present technique can save time, thereby increasing efficiency and reducing cost. The present technique involves the utilization of cell-feature metrics to accurately make decisions on the degree to which individual cells are "good" or "bad" candidates for patch clamping. These metrics include position coordinates (x,y) in the image plane, major-axis length, minor-axis length, area, elongation, roundness, smoothness, angle of orientation, and degree of inclusion in the field of view. The present technique does not require any special hardware beyond commercially available, off-the-shelf patch-clamping hardware: A standard patchclamping microscope system with an attached CCD camera, a personal computer with an imagedata- processing board, and some experience in utilizing imagedata- processing software are all that are needed. A cell image is first captured by the microscope CCD camera and image-data-processing board, then the image data are analyzed by software that implements the present machine-vision technique. This analysis results in the identification of cells that are "good" candidates for patch clamping (see figure). Once a "good" cell is identified, a patch clamp can be effected by an automated patchclamping apparatus or by a human operator. This technique has been shown to enable reliable identification of "good" and "bad" candidate cells for patch clamping. The ultimate goal in further development of this technique is to combine artificial-intelligence processing with instrumentation and controls in order to produce a complete "turnkey" automated patch-clamping system capable of accurately and reliably patch clamping cells with a minimum intervention by a human operator. Moreover, this technique can be adapted to virtually any cellular-analysis procedure that includes repetitive operation of microscope hardware by a human.

McDowell, Mark↗