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At least 1,153 records · Page 64

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NASA NTRS1978

A Schottky-barrier solar cell on sliced polycrystalline GaAs

Antireflecting-metal-oxide-semiconductor (AMOS) technology has been applied to sliced wafers of polycrystalline GaAs having grain sizes of about 100 microns. Simulated AM1 sunlight efficiencies up to 14% were obtained, and studies using the scanning electron microscope showed that grain boundaries have a minimal effect on short-circuit current density. However, current-voltage characteristics show some influence on open-circuit voltage.

Yeh, Y. C. M.↗

NASA NTRS1975

Space-charge-limited solid-state triode

A solid-state triode is provided from a wafer of nearinstrinsic semiconductor material sliced into filaments of rectangular cross section. Before slicing, emitter and collector regions are formed on the narrow sides of the filaments, and after slicing gate regions are formed in arrow strips extending longitudinally along the midsections of the wide sides of the filaments. Contacts are then formed on the emitter, collector and gate regions of each filament individually for a single filament device, or in parallel for an array of filament devices to increase load current.

Shumka, A.↗

NASA NTRS1978

LSSA large area silicon sheet task continuous Czochralski process development

A Czochralski crystal growing furnace was converted to a continuous growth facility by installation of a premelter to provide molten silicon flow into the primary crucible. The basic furnace is operational and several trial crystals were grown in the batch mode. Numerous premelter configurations were tested both in laboratory-scale equipment as well as in the actual furnace. The best arrangement tested to date is a vertical, cylindrical graphite heater containing small fused silicon test tube liner in which the incoming silicon is melted and flows into the primary crucible. Economic modeling of the continuous Czochralski process indicates that for 10 cm diameter crystal, 100 kg furnace runs of four or five crystals each are near-optimal. Costs tend to asymptote at the 100 kg level so little additional cost improvement occurs at larger runs. For these conditions, crystal cost in equivalent wafer area of around $20/sq m exclusive of polysilicon and slicing was obtained.

Rea, S. N.↗

NASA NTRS1979

Industrialization study, phase 2

The potentials and requirements of advanced photovoltaic technologies still in their early developmental stages were evaluated and compared to the present day single crystal silicon wafer technology and to each other. The major areas of consideration include polycrystalline and amorphous silicon, single crystal and polycrystalline gallium arsenide, and single crystal and polycrystalline cadmium sulfide. A rank ordering of the advanced technologies is provided. The various ranking schemes were based upon present-day efficiency levels, their stability and long-term reliability prospects, material availability, capital investments both at the laboratory and production level, and associated variable costs. An estimate of the timing of the possible readiness of these advanced technologies for technology development programs and industrialization is presented along with a set of recommended government actions concerning the various advanced technologies.

Source record↗

NASA NTRS1979

Development and fabrication of improved power transistor switches

A new class of high-voltage power transistors was achieved by adapting present interdigitated thyristor processing techniques to the fabrication of npn Si transistors. Present devices are 2.3 cm in diameter and have V sub CEO (sus) in the range of 400 to 600V. V sub CEO (sus) = 450V devices were made with an (h sub FE)(I sub C) product of 900A at V sub CE = 2.5V. The electrical performance obtained was consistent with the predictions of an optimum design theory specifically developed for power switching transistors. The device design, wafer processing, and assembly techniques are described. Experimental measurements of the dc characteristics, forward SOA, and switching times are included. A new method of characterizing the switching performance of power transistors is proposed.

Hower, P. L.↗

NASA NTRS1978

Development of Low-cost, High Energy-per-unit-area Solar Cell Modules

The development of two hexagonal solar cell process sequences, a laserscribing process technique for scribing hexagonal and modified hexagonal solar cells, a large through-put diffusion process, and two surface macrostructure processes suitable for large scale production is reported. Experimental analysis was made on automated spin-on anti-reflective coating equipment and high pressure wafer cleaning equipment. Six hexagonal solar cell modules were fabricated. Also covered is a detailed theoretical analysis on the optimum silicon utilization by modified hexagonal solar cells.

Jones, G. T.↗

NASA NTRS1979

Development of Pulsed Processes for the Manufacture of Solar Cells

The development status of the process based upon ion implantation for the introduction of junctions and back surface fields is described. A process sequence is presented employing ion implantation and pulse processing. Efforts to improve throughout and descrease process element costs for furnace annealing are described. Design studies for a modular 3,000 wafer per hour pulse processor are discussed.

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NASA NTRS1979

Effects of Impurities and Processing on Silicon Solar Cells, Phase 3

Results of the 14th quarterly report are presented for a program designed to assess the effects of impurities, thermochemical processes and any impurity process interactions on the performance of terrestrial silicon solar cells. The Phase 3 effort encompasses: (1) potential interactions between impurities and thermochemical processing of silicon; (2) impurity-cell performance relationships in n-base silicon; (3) effect of contaminants introduced during silicon production, refining or crystal growth on cell performance; (4) effects of nonuniform impurity distributions in large area silicon wafers; and (5) a preliminary study of the permanence of impurity effects in silicon solar cells.

Hopkins, R. H.↗

NASA NTRS1979

Development of non-volatile semiconductor memory

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Heikkila, W. W.↗

NASA NTRS1979

Process Development for Automated Solar Cell and Module Production. Task 4: Automated Array Assembly

A baseline sequence for the manufacture of solar cell modules was specified. Starting with silicon wafers, the process goes through damage etching, texture etching, junction formation, plasma edge etch, aluminum back surface field formation, and screen printed metallization to produce finished solar cells. The cells were then series connected on a ribbon and bonded into a finished glass tedlar module. A number of steps required additional developmental effort to verify technical and economic feasibility. These steps include texture etching, plasma edge etch, aluminum back surface field formation, array layup and interconnect, and module edge sealing and framing.

Source record↗

NASA NTRS1979

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Silicon Solar Array Project

Tests on mineral oil slurries show that the potential for workability and low cost is present. However, slurries tested to date which had sufficient lubricity exhibited wafer breakage problems near the end of the run for as-yet unknown reasons. The first test of the large prototype saw under cutting force control was largely successful in that the controller worked perfectly. Unfortunately a technique error (excessive stroke shortening) caused blade breakage and low yield. The latest run of the large saw pointed up the fact that an indication of end-of-stoke vertical motion, or bounce, is necessary. A circuit to provide such indication was fabricated and installed. Preliminary tests show it to be excessively noise sensitive; therefore, work on grounding and shielding to reduce this sensitivity is in progress.

Fleming, J. R.↗

NASA NTRS1979

Shock isolator for operating a diode laser on a closed-cycle refrigerator

A diode laser mounted within a helium refrigerator is mounted using a braided copper ground strap which provides good impact shock isolation from the refrigerator cold-tip while also providing a good thermal link to the cold-tip. The diode mount also contains a rigid stand-off assembly consisting of alternate sections of nylon and copper which serve as cold stations to improve thermal isolation from the vaccum housing mounting structure. Included in the mount is a Pb-In alloy wafer inserted between the cold-tip and the diode to damp temperature fluctuations occurring at the cold-tip.

Jennings, D. E.↗

NASA NTRS1979

Silicon Materials Task of the Low Cost Solar Array Project, Phase 3. Effect of Impurities and Processing on Silicon Solar Cells

The effects of impurities, various thermochemical processes, and any impurity process interactions on the performance of terrestrial silicon solar cells are defined. Determinations of the segregation coefficients of tungsten, tantalum, and cobalt for the Czochralski pulling of silicon single crystals are reported. Sensitive neutron activation analysis was used to determine the metal impurity content of the silicon while atomic absorption was used to measure the metal content of the residual liquid from which the doped crystals were grown. Gettering of Ti doped silicon wafers improved cell performance by one to two percent for the highest temperatures and longest times. The HCl is more effective than POCl3 treatments for deactivating Ti but POCl3 and HCl produced essentially identical results for Mo or Fe.

Hopkins, R. H.↗

NASA NTRS1978

Array Automated Assembly Task Low Cost Silicon Solar Array Project, Phase 2

Progress in the development of solar cells and module process steps for low-cost solar arrays is reported. Specific topics covered include: (1) a system to automatically measure solar cell electrical performance parameters; (2) automation of wafer surface preparation, printing, and plating; (3) laser inspection of mechanical defects of solar cells; and (4) a silicon antireflection coating system. Two solar cell process steps, laser trimming and holing automation and spray-on dopant junction formation, are described.

Rhee, S. S.↗

NASA NTRS1979

High efficiency cell geometry

A new silicon solar cell is described which has an array of small-area conduction paths to transport current directly through the wafer to metal electrodes on the back. This design eliminates grid shadowing and many of the other losses inherent in conventional cells. Early experimental units without texturing or antireflection coatings show 13.3% efficiency under air-mass-one illumination insolation.

Hall, R. N.↗

NASA NTRS1979

Design, processing and testing of LSI arrays: Hybrid microelectronics task

Mathematical cost factors were generated for both hybrid microcircuit and printed wiring board packaging methods. A mathematical cost model was created for analysis of microcircuit fabrication costs. The costing factors were refined and reduced to formulae for computerization. Efficient methods were investigated for low cost packaging of LSI devices as a function of density and reliability. Technical problem areas such as wafer bumping, inner/outer leading bonding, testing on tape, and tape processing, were investigated.

Himmel, R. P.↗

NASA NTRS1979

Transport of majority and minority carriers in 2-micron-diameter Pt-GaAs Schottky barriers

An experimental study of small area (2-micron diameter) Pt-GaAs Schottky barrier diodes has been made, by using a wafer chip with a matrix of these diodes lying within approximately a minority carrier diffusion length of one another. Using one diode as collector and another as emitter, transistor measurements indicated that the dominant contribution to the current is the majority-carrier thermionic field emission current for large forward-bias voltage of the emitter junction (V-EB no less than about 0.4 V), whereas the smaller forward-bias (V-EB no greater than about 0.4 V) recombination in the space-charge region was most important. The minority carrier injection ratio is measurable only for large forward-bias voltages, decreasing from about 0.02 to 0.00001 as VEB increases from 0.5 to 1.0 V. The minority carrier diffusion length was measured to be about 1.3 microns. These results are of considerable significance for the understanding and optimization of the performance of these devices as classical detectors and mixers.

Chan, E. Y.↗

NASA NTRS1978

Trapping effects in irradiated and avalanche-injected MOS capacitors

The trapping parameters for holes, and for electrons in the presence of trapped holes, have been measured from a set of wafers with different oxide thickness processed under controlled conditions. The trap cross-sections and densities indicate at least three trap species, including an interfacial species, a dominant bulk species which is determined to tail off from the silicon interface, and a third, lower density bulk species that is distributed throughout the oxide.

Bakowski, M.↗