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At least 1,153 records · Page 64

HOLOMEM, optical mass memory investigations, volume 1

Research and design activities in support of the development of a 10 to the 12th power-bit holographic read/write optical mass memory (HOLOMEM) with some moving parts for space applications are summarized. The report consists of four sections: (1) a general introduction, which includes a summary of key accomplishments and the principal conclusions of the study; (2) a comprehensive analysis of alternative HOLOMEM system concepts; (3) a discussion of important design and tradeoff considerations related to the fabrication, test, and evaluation of a breadboard holographic recorder/reproducer; and (4) a summary of experimental data generated to define the holographic recording performance of two quasi-commercial photoplastic recording films.

Roberts, H. N.↗

DIGIMEN, optical mass memory investigations, volume 2

The DIGIMEM phase of the Optical Mass Memory Investigation Program addressed problems related to the analysis, design, and implementation of a direct digital optical recorder/reproducer. Effort was placed on developing an operational archival mass storage system to support one or more key NASA missions. The primary activity of the DIGIMEM program phase was the design, fabrication, and test and evaluation of a breadboard digital optical recorder/reproducer. Starting with technology and subsystem perfected during the HOLOMEM program phase, a fully operational optical spot recording breadboard that met or exceeded all program goals was evaluated. A thorough evaluation of several high resolution electrophotographic recording films was performed and a preliminary data base management/end user requirements survey was completed.

Source record↗

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

Klute, A.↗

Electrical Evaluation of RCA MWS5501D Random Access Memory, Volume 2, Appendix a

The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. The address access time, address readout time, the data hold time, and the data setup time are some of the results surveyed.

Klute, A.↗

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 3, Appendix B

The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. The test values for the output voltage, average input current, the supply current and the leakage current are presented.

Klute, A.↗

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 4, Appendix C

The electrical characterization and qualification test results are presented for the RCA MWS5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Statistical analysis data is supplied along with write pulse width, read cycle time, write cycle time, and chip enable time data.

Klute, A.↗

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 5, Appendix D

The electrical characterization and qualification test results are presented for the RCA MWS 5001D random access memory. The tests included functional tests, AC and DC parametric tests, AC parametric worst-case pattern selection test, determination of worst-case transition for setup and hold times, and a series of schmoo plots. Average input high current, worst case input high current, output low current, and data setup time are some of the results presented.

Klute, A.↗

Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

Klute, A.↗

A /31,15/ Reed-Solomon Code for large memory systems

This paper describes the encoding and the decoding of a (31,15) Reed-Solomon Code for multiple-burst error correction for large memory systems. The decoding procedure consists of four steps: (1) syndrome calculation, (2) error-location polynomial calculation, (3) error-location numbers calculation, and (4) error values calculation. The principal features of the design are the use of a hardware shift register for both high-speed encoding and syndrome calculation, and the use of a commercially available (31,15) decoder for decoding Steps 2, 3 and 4.

Lim, R. S.↗

Proton upsets in LSI memories in space

Two types of large scale integrated dynamic random access memory devices were tested and found to be subject to soft errors when exposed to protons incident at energies between 18 and 130 MeV. These errors are shown to differ significantly from those induced in the same devices by alphas from an Am-241 source. There is considerable variation among devices in their sensitivity to proton-induced soft errors, even among devices of the same type. For protons incident at 130 MeV, the soft error cross sections measured in these experiments varied from 10 to the -8th to 10 to the -6th sq cm/proton. For individual devices, however, the soft error cross section consistently increased with beam energy from 18-130 MeV. Analysis indicates that the soft errors induced by energetic protons result from spallation interactions between the incident protons and the nuclei of the atoms comprising the device. Because energetic protons are the most numerous of both the galactic and solar cosmic rays and form the inner radiation belt, proton-induced soft errors have potentially serious implications for many electronic systems flown in space.

Mcnulty, P. J.↗

An 8 x 10 to the 5th bit bubble memory cell for spacecraft applications

A multiple chip magnetic bubble memory cell design developed for NASA embodies the low power, low weight, environmental tolerance and reliability necessary for successful operation in spacecraft launch and mission environments. Packaging of multiple chips in a common magnetic bias, drive coil assembly reduces weight and volume overhead per chip and also reduces the number of coil drive components required. This 8 x 10 to the 5th bit cell is conduction cooled and provides a metal and ceramic sealed hermetic chip environment.

Becker, F. J.↗

A current access, self-structured, multilayered bubble domain memory

Preliminary experimental results are reported on a self-structured, multilayer bubble memory with buried data layer. Stripe domains are used to move carrier bubbles by magnetostatic coupling. An expression is derived for that coupling as a function of thickness of the GGG separation layer. Experimental values of coupling are given as a function of bias field. An expression for stripe curvature as a function of bias field is derived. The performance of seven different current access stripe propagation circuits is reported.

Stermer, R. L., Jr.↗

Optical mass memory system (AMM-13). AMM/DBMS interface control document

The baseline for external interfaces of a 10 to the 13th power bit, optical archival mass memory system (AMM-13) is established. The types of interfaces addressed include data transfer; AMM-13, Data Base Management System, NASA End-to-End Data System computer interconnect; data/control input and output interfaces; test input data source; file management; and facilities interface.

Bailey, G. A.↗

The NEEDS Data Base Management and Archival Mass Memory System

A Data Base Management System and an Archival Mass Memory System are being developed that will have a 10 to the 12th bit on-line and a 10 to the 13th off-line storage capacity. The integrated system will accept packetized data from the data staging area at 50 Mbps, create a comprehensive directory, provide for file management, record the data, perform error detection and correction, accept user requests, retrieve the requested data files and provide the data to multiple users at a combined rate of 50 Mbps. Stored and replicated data files will have a bit error rate of less than 10 to the -9th even after ten years of storage. The integrated system will be demonstrated to prove the technology late in 1981.

Bailey, G. A.↗

Content-addressable read/write memories for image analysis

The commonly encountered image analysis problems of region labeling and clustering are found to be cases of search-and-rename problem which can be solved in parallel by a system architecture that is inherently suitable for VLSI implementation. This architecture is a novel form of content-addressable memory (CAM) which provides parallel search and update functions, allowing speed reductions down to constant time per operation. It has been proposed in related investigations by Hall (1981) that, with VLSI, CAM-based structures with enhanced instruction sets for general purpose processing will be feasible.

Snyder, W. E.↗

An iterative approach to region growing using associative memories

Region growing, often given as a classical example of the recursive control structures used in image processing which are often awkward to implement in hardware where the intent is the segmentation of an image at raster scan rates, is addressed in light of the postulate that any computation which can be performed recursively can be performed easily and efficiently by iteration coupled with association. Attention is given to an algorithm and hardware structure able to perform region labeling iteratively at scan rates. Every pixel is individually labeled with an identifier which signifies the region to which it belongs. Difficulties otherwise requiring recursion are handled by maintaining an equivalence table in hardware transparent to the computer, which reads the labeled pixels. A simulation of the associative memory has demonstrated its effectiveness.

Snyder, W. E.↗

Optical Mass Memory System Specification

Specifications given for computer controlled optical mass memory system that stores and retrieves data from silver halide fiches 148-mmsquare and 7 mils (0.18mm) thick at user bit density of 30 Mbit/in. 2 (4.7 Mbit/cm2) with uncorrectable bit-error rate of 10 to negative 9th power or less. Allows for expansion to 10 the 15th power bit capacity.

Source record↗

Memory-Metal Stepping Motor

Compact stepping motor for applications requiring high torque at slow speeds made with helical spring clutch and electrically-heated memory-metal actuator.

Jamieson, R. S.↗