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At least 1,135 records · Page 63

Precise orbit determination of high-earth elliptical orbiters using differenced Doppler and ranging measurements

Recent advances in NASA's Deep Space Network station calibration methods have led to renewed interest in the use of differenced radiometric data types for interplanetary navigation, particularly differenced Doppler and range. An orbit determination error analysis which compares the performance of these differenced data types when used in concert with conventional two-way Doppler for precise navigation of high-earth orbiters is described. Three highly elliptical orbits are investigated, with apogee heights on the order of 20,000 km, 70,000 km, and 156,000 km. The analysis assumes that each orbiter's downlink antenna has no ground footprint limitation in the near apogee regime. Results indicate that the most significant navigational accuracy improvements are seen for the lowest-altitude orbit by using differenced Doppler measurements in conjunction with two-way Doppler. The results for the two higher-altitude orbits, although less dramatic, suggest that accuracy improvements can also be achieved when differenced range measurements are combined with two-way Doppler.

Estefan, Jeff A.↗

Studies on distributed sensing and processing for the control of large flexible spacecraft

Technology is being developed to process signals from distributed sensors using distributed computations. These distributed sensors provide a new feedback capability for vibration control that has not been exploited. Additionally, the sensors proposed are of an optical and distributed nature and could be employed with known techniques of distributed optical computation (Fourier optics, etc.) to accomplish the control system functions of filtering and regulation in a distributed computer. This paper reviews a procedure for the analytic design of control systems for this application. For illustration, the procedure is applied to the problem of suppressing the vibrations of a simply supported beam. A simulator has been developed to study the effects of sensor and processing errors. An extensive study of the effects of these errors on estimation and regulation performance is presented.

Montgomery, Raymond C.↗

Design of a monopulse SAR system to determine elevation angles

Terrain height variations in mountainous areas cause problems in radiometric corrections of synthetic aperture radar (SAR) images. To determine the elevation angle and the height at the different parts of an image, an application of the monopulse principle is proposed. From the ratios of images radiometrically modulated by the difference and sum antenna pattern in range it is possible to calculate the appropriate elevation angle at any point in the image. Design considerations for a corresponding airborne SAR-system are presented, and some estimates of error influences (e.g., ambiguities), expected performance and precision in topographic mapping are given.

Oettl, H.↗

Advanced satellite communication system

The objective of this research program was to develop an innovative advanced satellite receiver/demodulator utilizing surface acoustic wave (SAW) chirp transform processor and coherent BPSK demodulation. The algorithm of this SAW chirp Fourier transformer is of the Convolve - Multiply - Convolve (CMC) type, utilizing off-the-shelf reflective array compressor (RAC) chirp filters. This satellite receiver, if fully developed, was intended to be used as an on-board multichannel communications repeater. The Advanced Communications Receiver consists of four units: (1) CMC processor, (2) single sideband modulator, (3) demodulator, and (4) chirp waveform generator and individual channel processors. The input signal is composed of multiple user transmission frequencies operating independently from remotely located ground terminals. This signal is Fourier transformed by the CMC Processor into a unique time slot for each user frequency. The CMC processor is driven by a waveform generator through a single sideband (SSB) modulator. The output of the coherent demodulator is composed of positive and negative pulses, which are the envelopes of the chirp transform processor output. These pulses correspond to the data symbols. Following the demodulator, a logic circuit reconstructs the pulses into data, which are subsequently differentially decoded to form the transmitted data. The coherent demodulation and detection of BPSK signals derived from a CMC chirp transform processor were experimentally demonstrated and bit error rate (BER) testing was performed. To assess the feasibility of such advanced receiver, the results were compared with the theoretical analysis and plotted for an average BER as a function of signal-to-noise ratio. Another goal of this SBIR program was the development of a commercial product. The commercial product developed was an arbitrary waveform generator. The successful sales have begun with the delivery of the first arbitrary waveform generator.

Staples, Edward J.↗

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

Design of an anti-Rician-fading modem for mobile satellite communication systems

To design a demodulator applicable to mobile satellite communication systems using differential phase shift keying modulation, we have developed key technologies including an anti-Rician-fading demodulation scheme, an initial acquisition scheme, automatic gain control (AGC), automatic frequency control (AFC), and bit timing recovery (BTR). Using these technologies, we have developed one-chip digital signal processor (DSP) modem for mobile terminal, which is compact, of light weight, and of low power consumption. Results of performance test show that the developed DSP modem achieves good performance in terms of bit error ratio in mobile satellite communication environment, i.e., Rician fading channel. It is also shown that the initial acquisition scheme acquires received signal rapidly even if the carrier-to-noise power ratio (CNR) of the received signal is considerably low.

Kojima, Toshiharu↗

Architecture and implementation considerations of a high-speed Viterbi decoder for a Reed-Muller subcode

The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.

Lin, Shu↗

A Wide Bandwidth Model for the Electrical Impedance of Magnetic BearingS

Magnetic bearings are often designed using magnetic circuit theory. When these bearings are built, however, effects not included in the usual circuit theory formulation have a significant influence on bearing performance. Two significant sources of error in the circuit theory approach are the neglect of leakage and fringing effects and the neglect of eddy current effects. This work formulates an augmented circuit model in which eddy current and flux leakage and fringing effects are included. Through the use of this model, eddy current power losses and actuator bandwidth can be derived. Electrical impedance predictions from the model are found to be in good agreement with experimental data from a typical magnetic bearing.

Meeker, David C.↗

Utilizing Flight Data to Update Aeroelastic Stability Estimates

Stability analysis of high performance aircraft must account for errors in the system model. A method for computing flutter margins that incorporates flight data has been developed using robust stability theory. This paper considers applying this method to update flutter margins during a post-flight or on-line analysis. Areas of modeling uncertainty that arise when using flight data with this method are investigated. The amount of conservatism in the resulting flutter margins depends on the flight data sets used to update the model. Post-flight updates of flutter margins for an F/A-18 are presented along with a simulation of on-line updates during a flight test.

Lind, Rick↗

Human Reliability Analysis: An Overview

Human/process error is potentially a large contributor to failures of aerospace systems. For some systems, such as the space shuttle main engine, large amounts of data are available, and accurate failure rates can be determined empirically. For such systems, the human error is implicit in the empirical failure rate and does not need to be quantified separately. However, for other systems, such as the solid rocket boosters, large amounts of data are not available and the failure rates must be determined by more theoretical means. When empirical data is lacking, structural models and engineering judgment must be employed. In this case, the human/process error must be modeled explicitly. An extensive literature review was performed to determine what methods already exist for modeling human error for aerospace systems. No methods that apply directly were found, although there are a number of methods that have been developed specifically for the nuclear power industry that could probably be modified for space applications. The results of the literature review are presented, as well as recommendations for future research.

Navard, Sharon E.↗

In-Flight Assessment of a Pursuit Guidance Display Format for Manually Flown Precision Instrument Approaches

In-flight evaluations of a pursuit guidance display system for manually flown precision instrument approaches were performed. The guidance system was integrated into the RASCAL JUH-60A Black Hawk helicopter. The applicability of the pursuit guidance disp1aFs to the operation of Runway Independent Aircraft (RIA) is made evident because the displays allow the pilot to fly a complex, multi-segment, descending, decelerating approach trajectory. The complex trajectory chosen for this in-flight assessment began from a downwind abeam position at 110 knots and was hand-flown to a 50 ft decision altitude at 40 knots using a rate-command/attitude-hold plus turn-coordination control system. The elements of the pursuit guidance format displayed on a 10-inch liquid crystal display (LCD) flat panel consisted of a flightpath vector and a "leader" aircraft as the pursuit guidance element. Approach guidance was based primarily on carrier-phase differential Global Positioning System (GPS) navigation, and secondarily on both medium accuracy inertial navigation unit states and air data computer states. Required Navigation Performance (RNP) concepts were applied to the construction of display elements such as lateral/vertical deviation indicators and a tunnel that indicated to the pilot, in real-time, the performance with respect to RNP error bounds. The results of the flight evaluations of the guidance display show that precise path control for operating within tight RNP boundaries (RNP 0.007NM/24ft for initial approach, RNP 0.008NM/19ft for intermediate approach, and RNP 0.002NM/9ft for final approach) is attainable with minimal to moderate pilot workload.

Moralez, Ernesto, III↗

Micro-Precision Interferometer: Pointing Control System

This paper describes the development of the wavefront tilt (pointing) control system for the JPL Micro-Precision Interferometer (MPI). This control system employs piezo-electric actuators and a digital imaging sensor with feedback compensation to reject errors in instrument pointing. Stringent performance goals require large feedback, however, several characteristics of the plant tend to restrict the available bandwidth. A robust 7th-order wavefront tilt control system was successfully implemented on the MPI instrument, providing sufficient disturbance rejection performance to satisfy the established interference fringe visibility.

Micro-Precision Pointing↗

Closed-Loop Performance Measures for Flight Controllers Subject to Neutron-Induced Upsets

It has been observed that atmospheric neutrons can produce single event upsets in digital flight control hardware. The phenomenon has been studied extensively at the chip level, and now system level experiments are underway. In this paper analytical closed-loop performance measures for the tracking error are developed for a plant that is stabilized by a recoverable computer system subject to neutron induced upsets. The underlying model is a Markov jump-linear system with process noise. The steady-state tracking error is expressed in terms of a generalized observability Gramian.

Gray, W. Steven↗

System Engineering the Space Infrared Interferometric Telescope (SPIRIT)

The Space Infrared Interferometric Telescope (SPIRIT) was designed to accomplish three scientific objectives: (1) learn how planetary systems form from protostellar disks and how they acquire their inhomogeneous chemical composition; (2) characterize the family of extrasolar planetary systems by imaging the structure in debris disks to understand how and where planets of different types form; and (3) learn how high-redshift galaxies formed and merged to form the present-day population of galaxies. SPIRIT will accomplish these objectives through infrared observations with a two aperture interferometric instrument. This paper gives an overview of SPIRIT design and operation, and how the three design cycle concept study was completed. The error budget for several key performance values allocates tolerances to all contributing factors, and a performance model of the spacecraft plus instrument system demonstrates meeting those allocations with margin.

Hyde, Tristram T.↗