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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,135 records · Page 63
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

Development and evaluation of a fault-tolerant multiprocessor (FTMP) computer. Volume 4: FTMP executive summary

The FTMP architecture is a high reliability computer concept modeled after a homogeneous multiprocessor architecture. Elements of the FTMP are operated in tight synchronism with one another and hardware fault-detection and fault-masking is provided which is transparent to the software. Operating system design and user software design is thus greatly simplified. Performance of the FTMP is also comparable to that of a simplex equivalent due to the efficiency of fault handling hardware. The FTMP project constructed an engineering module of the FTMP, programmed the machine and extensively tested the architecture through fault injection and other stress testing. This testing confirmed the soundness of the FTMP concepts.

Smith, T. B., III↗
NASA NTRS1996

An Evaluation of Architectural Platforms for Parallel Navier-Stokes Computations

We study the computational, communication, and scalability characteristics of a computational fluid dynamics application, which solves the time accurate flow field of a jet using the compressible Navier-Stokes equations, on a variety of parallel architecture platforms. The platforms chosen for this study are a cluster of workstations (the LACE experimental testbed at NASA Lewis), a shared memory multiprocessor (the Cray YMP), and distributed memory multiprocessors with different topologies - the IBM SP and the Cray T3D. We investigate the impact of various networks connecting the cluster of workstations on the performance of the application and the overheads induced by popular message passing libraries used for parallelization. The work also highlights the importance of matching the memory bandwidth to the processor speed for good single processor performance. By studying the performance of an application on a variety of architectures, we are able to point out the strengths and weaknesses of each of the example computing platforms.

Jayasimha, D. N.↗
NASA NTRS1982

Automatically Reconfigurable Computer

Modular system changes its architecture to maximize either reliability or capacity. Reconfigurable computer is assembled from four kinds of modules: organizer/scheduler, memory, input/output processor, and central processor. Reconfiguration is initiated by a signal from a control panel or by fault interrupt from one of the modules.

Source record↗
DOE OSTI2017

Graphics processing unit accelerated phase field dislocation dynamics: Application to bi-metallic interfaces

We present the first high-performance computing implementation of the meso-scale phase field dislocation dynamics (PFDD) model on a graphics processing unit (GPU)-based platform. The implementation takes advantage of the portable OpenACC standard directive pragmas along with Nvidia's compute unified device architecture (CUDA) fast Fourier transform (FFT) library called CUFFT to execute the FFT computations within the PFDD formulation on the same GPU platform. The overall implementation is termed ACCPFDD-CUFFT. The package is entirely performance portable due to the use of OPENACC-CUDA inter-operability, in which calls to CUDA functions are replaced with the OPENACC data regions for a host central processing unit (CPU) and device (GPU). A comprehensive benchmark study has been conducted, which compares a number of FFT routines, the Numerical Recipes FFT (FOURN), Fastest Fourier Transform in the West (FFTW), and the CUFFT. The last one exploits the advantages of the GPU hardware for FFT calculations. The novel ACCPFDD-CUFFT implementation is verified using the analytical solutions for the stress field around an infinite edge dislocation and subsequently applied to simulate the interaction and motion of dislocations through a bi-phase copper-nickel (Cu–Ni) interface. It is demonstrated that the ACCPFDD-CUFFT implementation on a single TESLA K80 GPU offers a 27.6X speedup relative to the serial version and a 5X speedup relative to the 22-multicore Intel Xeon CPU E5-2699 v4 @ 2.20 GHz version of the code.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Evaluation of Portable Programming Models to Accelerate LArTPC Detector Simulations

The Liquid Argon Time Projection Chamber (LArTPC) technology is widely used in high energy physics experiments, including the upcoming Deep Underground Neutrino Experiment (DUNE). Accurately simulating LArTPC detector responses is essential for analysis algorithm development and physics model interpretations. Accurate LArTPC detector response simulations are computationally demanding, and can become a bottleneck in the analysis workflow. Compute devices such as General-Purpose Graphics Processing Units (GPGPUs) have the potential to substantially accelerate simulations compared to traditional CPU-only processing. The software development for these compute accelerators often carries the cost of specialized code refactorization and porting to match the target hardware architecture. With the rapid evolution and increased diversity of the computer architecture landscape, it is highly desirable to have a portable solution that also maintains reasonable performance. We report our ongoing effort in evaluating Kokkos as a basis for this portable programming model using LArTPC simulations in the context of the Wire-Cell Toolkit, a C++ library for LArTPC simulations, data analysis, reconstruction and visualization.

47 OTHER INSTRUMENTATION↗
DOE OSTI2014

Computational Nanophotonics: Model Optical Interactions and Transport in Tailored Nanosystem Architectures

The program is directed toward development of new computational approaches to photoprocesses in nanostructures whose geometry and composition are tailored to obtain desirable optical responses. The emphasis of this specific program is on the development of computational methods and prediction and computational theory of new phenomena of optical energy transfer and transformation on the extreme nanoscale (down to a few nanometers).

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2023

Differentiable Neural Architecture, Mixed Precision and Accelerator Co-Search

Quantization, effective Neural Network architecture, and efficient accelerator hardware are three important design paradigms to maximize accuracy and efficiency. Mixed Precision Quantization is a process of assigning different precision to different Neural Network layers for optimized inference. Neural Architecture Search (NAS) is a process of automatically designing the neural network for a task and can also be extended to search for the precision of each weight and activation matrix. In this paper, we develop the following three methods: (i) Fast Differentiable Hardware-aware Mixed Precision Quantization Search method to find optimal precision, (ii) Joint Differentiable hardware-aware Architecture and Mixed Precision Quantization Co-search, (iii) Joint Accelerator, Architecture, and Precision triple co-search to find best possibilities in all the three worlds. We demonstrate the effectiveness of our proposed methods targeting Bitfusion accelerator by searching mixed precision models on MobilenetV2. We achieve better accuracy-latency trade-off models than the manually designed and previously proposed search methods.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

GPU-accelerated multitiered iterative phasing algorithm for fluctuation X-ray scattering

The multitiered iterative phasing (MTIP) algorithm is used to determine the biological structures of macromolecules from fluctuation scattering data. It is an iterative algorithm that reconstructs the electron density of the sample by matching the computed fluctuation X-ray scattering data to the external observations, and by simultaneously enforcing constraints in real and Fourier space. This paper presents the first ever MTIP algorithm acceleration efforts on contemporary graphics processing units (GPUs). The Compute Unified Device Architecture (CUDA) programming model is used to accelerate the MTIP algorithm on NVIDIA GPUs. The computational performance of the CUDA-based MTIP algorithm implementation outperforms the CPU-based version by an order of magnitude. Furthermore, the Heterogeneous-Compute Interface for Portability (HIP) runtime APIs are used to demonstrate portability by accelerating the MTIP algorithm across NVIDIA and AMD GPUs.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1989

NASA Workshop on Computational Structural Mechanics 1987, part 1

Topics in Computational Structural Mechanics (CSM) are reviewed. CSM parallel structural methods, a transputer finite element solver, architectures for multiprocessor computers, and parallel eigenvalue extraction are among the topics discussed.

Sykes, Nancy P.↗
NASA NTRS1999

BIO-Plex Information System Concept

This paper describes a suggested design for an integrated information system for the proposed BIO-Plex (Bioregenerative Planetary Life Support Systems Test Complex) at Johnson Space Center (JSC), including distributed control systems, central control, networks, database servers, personal computers and workstations, applications software, and external communications. The system will have an open commercial computing and networking, architecture. The network will provide automatic real-time transfer of information to database server computers which perform data collection and validation. This information system will support integrated, data sharing applications for everything, from system alarms to management summaries. Most existing complex process control systems have information gaps between the different real time subsystems, between these subsystems and central controller, between the central controller and system level planning and analysis application software, and between the system level applications and management overview reporting. An integrated information system is vitally necessary as the basis for the integration of planning, scheduling, modeling, monitoring, and control, which will allow improved monitoring and control based on timely, accurate and complete data. Data describing the system configuration and the real time processes can be collected, checked and reconciled, analyzed and stored in database servers that can be accessed by all applications. The required technology is available. The only opportunity to design a distributed, nonredundant, integrated system is before it is built. Retrofit is extremely difficult and costly.

Jones, Harry↗
NASA NTRS2019

AladynPi – Adaptive Neural Network Molecular Dynamics Simulation Code with Physically Informed Potential: Computational Materials Mini-Application

This report provides an overview and description of commands used in the Computational Materials mini-application, AladynPi. AladynPi is an extension of a previously released mini-application, Aladyn (https://github.com/nasa/aladyn; Yamakov, V.I., and Glaessgen, E.H., NASA/TM-2018-220104). Aladyn and AladynPi are basic molecular dynamics codes written in FORTRAN 2003, which are designed to demonstrate the use of adaptive neural networks (ANNs) in atomistic simulations. The role of ANNs is to efficiently reproduce the very complex energy landscape resulting from the atomic interactions in materials with the accuracy of the more expensive quantum mechanics-based calculations. The ANN is trained on a large set of atomic structures calculated using the density functional theory method. An input for the ANN is a set of structure coefficients, characterizing the local atomic environment of each atom, for which the atomic energy is obtained in the ANN inference process. In Aladyn, the ANN gives directly the energy of interatomic interactions. In AladynPi, the ANN gives optimized parameters for a predefined empirical function, known as bond-order-potential (BOP). The parameterized BOP function is then used to calculate the energy. AladynPi code is being released to serve as a training testbed for students and professors in academia to explore possible optimization algorithms for parallel computing on multicore central processing unit (CPU) computers or computers utilizing manycore architectures based on graphic processing units (GPUs). The effort is supported by the High Performance Computing incubator (HPCi) project at NASA Langley Research Center.

Yamakov, Vesselin I.↗
NASA NTRSDate not supplied

Ray Tracing Techniques for the Characterization of Lunar Communication Architectures

This paper provides an overview of the computational techniques used to characterize the viability of different lunar architectures and their ability to provide communication services to the lunar surface. This analysis was done with modern ray tracing techniques that allow for the computations to be done on Graphics Processing Unit (GPU) clusters for a high level of parallelism and severe reduction in computation time. The ray tracing computations were done with the GPU platform Compute Unified Device Architecture (CUDA) provided by NVIDIA which utilizes general-purpose computing on graphics processing units (GPGPU). This new method provides the advantage of being able to characterize a much larger portion of the lunar surface due to its computational efficiency as well as providing a more accurate representation of elevation angle limits instead of the typical and often inaccurate elevation angle mask. The Lunar surface can now be characterized with metrics such as contact time, outage time, and received data rate. With these metrics, different proposed Lunar architectures can be rapidly evaluated. This reduction in computation time not only leads to more accurate results but allows these results to be obtained in a time frame that allows for the complete characterization of the trade space. It is expected that these different architecture comparisons will lead to a conclusive determination of the optimal Lunar architecture and will allow for future Lunar missions to operate as close to real time as possible. In addition, this computation method can be used to recreate visibility figures generated by previous methods but with an increased level of accuracy.

Thomas Montano↗
DOE OSTI2020

Optimal Renewable Resource Allocation and Load Scheduling of Resilient Communities

This paper presents a methodology for enhancing community resilience through optimal renewable resource allocation and load scheduling in order to minimize unserved load and thermal discomfort. The proposed control architecture distributes the computational effort and is easier to be scaled up than traditional centralized control. The decentralized control architecture consists of two layers: The community operator layer (COL) allocates the limited amount of renewable energy resource according to the power flexibility of each building. The building agent layer (BAL) addresses the optimal load scheduling problem for each building with the allowable load determined by the COL. Both layers are formulated as a model predictive control (MPC) based optimization. Simulation scenarios are designed to compare different combinations of building weighting methods and objective functions to provide guidance for real-world deployment by community and microgrid operators. The results indicate that the impact of power flexibility is more prominent than the weighting factor to the resource allocation process. Allocation based purely on occupancy status could lead to an increase of PV curtailment. Further, it is necessary for the building agent to have multi-objective optimization to minimize unserved load ratio and maximize comfort simultaneously.

model predictive control↗
NASA NTRS1987

Parallel computations and their impact on mechanics; Proceedings of the Symposium, ASME Winter Annual Meeting, Boston, MA, Dec. 13-18, 1987

The conference presents papers on parallel architectures and the programming environment, parallel numerical algorithms, structural mechanics applications, and fluid dynamics applications. Topics include concurrent computer architecture, the state-of-the-art in highly parallel computer systems, supercomputer programming environments, uniquely parallel algorithms, the parallel solution of nonlinear elliptic equations, highly parallel banded systems solvers, and optimal mapping of irregular finite element domains to parallel processors. Consideration is also given to parallel processing in finite element structural analysis, heirarchical parallelism in a finite element CFD algorithm, and a parallelized elliptic solver for reacting flows.

Noor, Ahmed K.↗
NASA NTRS2009

Sequential Principal Component Analysis -An Optimal and Hardware-Implementable Transform for Image Compression

This paper presents the JPL-developed Sequential Principal Component Analysis (SPCA) algorithm for feature extraction / image compression, based on "dominant-term selection" unsupervised learning technique that requires an order-of-magnitude lesser computation and has simpler architecture compared to the state of the art gradient-descent techniques. This algorithm is inherently amenable to a compact, low power and high speed VLSI hardware embodiment. The paper compares the lossless image compression performance of the JPL's SPCA algorithm with the state of the art JPEG2000, widely used due to its simplified hardware implementability. JPEG2000 is not an optimal data compression technique because of its fixed transform characteristics, regardless of its data structure. On the other hand, conventional Principal Component Analysis based transform (PCA-transform) is a data-dependent-structure transform. However, it is not easy to implement the PCA in compact VLSI hardware, due to its highly computational and architectural complexity. In contrast, the JPL's "dominant-term selection" SPCA algorithm allows, for the first time, a compact, low-power hardware implementation of the powerful PCA algorithm. This paper presents a direct comparison of the JPL's SPCA versus JPEG2000, incorporating the Huffman and arithmetic coding for completeness of the data compression operation. The simulation results show that JPL's SPCA algorithm is superior as an optimal data-dependent-transform over the state of the art JPEG2000. When implemented in hardware, this technique is projected to be ideally suited to future NASA missions for autonomous on-board image data processing to improve the bandwidth of communication.

Duong, Tuan A.↗
NASA NTRS1988

Semi-automatic process partitioning for parallel computation

On current multiprocessor architectures one must carefully distribute data in memory in order to achieve high performance. Process partitioning is the operation of rewriting an algorithm as a collection of tasks, each operating primarily on its own portion of the data, to carry out the computation in parallel. A semi-automatic approach to process partitioning is considered in which the compiler, guided by advice from the user, automatically transforms programs into such an interacting task system. This approach is illustrated with a picture processing example written in BLAZE, which is transformed into a task system maximizing locality of memory reference.

Koelbel, Charles↗