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All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

Compact, Reliable EEPROM Controller

A compact, reliable controller for an electrically erasable, programmable read-only memory (EEPROM) has been developed specifically for a space-flight application. The design may be adaptable to other applications in which there are requirements for reliability in general and, in particular, for prevention of inadvertent writing of data in EEPROM cells. Inadvertent writes pose risks of loss of reliability in the original space-flight application and could pose such risks in other applications. Prior EEPROM controllers are large and complex and do not provide all reasonable protections (in many cases, few or no protections) against inadvertent writes. In contrast, the present controller provides several layers of protection against inadvertent writes. The controller also incorporates a write-time monitor, enabling determination of trends in the performance of an EEPROM through all phases of testing. The controller has been designed as an integral subsystem of a system that includes not only the controller and the controlled EEPROM aboard a spacecraft but also computers in a ground control station, relatively simple onboard support circuitry, and an onboard communication subsystem that utilizes the MIL-STD-1553B protocol. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD- 1553B is commonly used in defense and space applications.) The intent was to both maximize reliability while minimizing the size and complexity of onboard circuitry. In operation, control of the EEPROM is effected via the ground computers, the MIL-STD-1553B communication subsystem, and the onboard support circuitry, all of which, in combination, provide the multiple layers of protection against inadvertent writes. There is no controller software, unlike in many prior EEPROM controllers; software can be a major contributor to unreliability, particularly in fault situations such as the loss of power or brownouts. Protection is also provided by a powermonitoring circuit.

Katz, Richard↗
NASA NTRS2010

SEU/SET Tolerant Phase-Locked Loops

The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!

Shuler, Robert L., Jr.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2012

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Vasile, Stefan↗
DOE OSTI2026

Short Circuit Detection and Voltage Sense for High Voltage Ionization Tube Power Supplies

Fermilab's PIP-II upgrade requires new rack-mounted power supplies for Beam Loss Monitor (BLM) ionization tubes compatible with the microTCA 4.1 standard, supporting high-side current measurement for short circuit detection, voltage sense telemetry, and low-side current measurement for beam loss readout. This work presents the design and preliminary schematic of such a supply. A resistive current sensing approach was chosen over inductive, optical, and Hall-effect alternatives for its independence from cable length and component availability. A 500 mΩ inline shunt steps the 2 kV common mode voltage down to roughly 70 V, producing a ~27 μV pulse during a short, which is amplified 500x, compared against a 14-bit DAC threshold, and latched to drive a fault line. Voltage sense steps the 2 kV output down at a 1V/1000V ratio, buffers it with a low bias current amplifier, and digitizes it via a 24-bit ADC over SPI. Onboard power is regulated from 12 V down to isolated 5 V and 3.3 V rails, with capacitive isolation on FPGA communication lines. Lumped parameter models were developed for the ionization tube (0.327 nF, 20 to 200 GΩ dynamic resistance) and the RG-58 coaxial cable to support the design. Component selection is complete and a preliminary schematic has been drawn in Altium Designer, forming the foundation for future prototyping and validation.

Yu, Kellen [Cornell U.]↗
NASA NTRS1987

Development of an LED display system for cross-track distance and velocity for Loran-C flight

The methodology for estimating cross-track velocity by combining rate-gyro and Loran-C data is illustrated in block diagrams. At present, preliminary analysis has established values for K sub 1, K sub 2, the parameters of the digital control loops. A computer program was written to implement a digital simulation of the system as illustrated. Given a model for the noise in the rate-gyro and Loran-C receiver, and their dynamic response, the simulation provides a working model to establish good control loop parameters. The layout of the LED display for flight testing of Loran-C approach flying, which was constructed during a visit to Langley Research Center, is shown. Four bar-graph LED displays are paired to provide cross-track distance and velocity from a Loran-C defined runway centerline. Two seven-segment LED displays are used to provide alphanumeric readout of range to touchdown and desired height. A metal case was built, a circuit board designed, and manufactured with the assistance of NASA Langley personnel.

Dogan, Norry↗
NASA NTRS2001

Accurate Time-Dependent Traveling-Wave Tube Model Developed for Computational Bit-Error-Rate Testing

The phenomenal growth of the satellite communications industry has created a large demand for traveling-wave tubes (TWT's) operating with unprecedented specifications requiring the design and production of many novel devices in record time. To achieve this, the TWT industry heavily relies on computational modeling. However, the TWT industry's computational modeling capabilities need to be improved because there are often discrepancies between measured TWT data and that predicted by conventional two-dimensional helical TWT interaction codes. This limits the analysis and design of novel devices or TWT's with parameters differing from what is conventionally manufactured. In addition, the inaccuracy of current computational tools limits achievable TWT performance because optimized designs require highly accurate models. To address these concerns, a fully three-dimensional, time-dependent, helical TWT interaction model was developed using the electromagnetic particle-in-cell code MAFIA (Solution of MAxwell's equations by the Finite-Integration-Algorithm). The model includes a short section of helical slow-wave circuit with excitation fed by radiofrequency input/output couplers, and an electron beam contained by periodic permanent magnet focusing. A cutaway view of several turns of the three-dimensional helical slow-wave circuit with input/output couplers is shown. This has been shown to be more accurate than conventionally used two-dimensional models. The growth of the communications industry has also imposed a demand for increased data rates for the transmission of large volumes of data. To achieve increased data rates, complex modulation and multiple access techniques are employed requiring minimum distortion of the signal as it is passed through the TWT. Thus, intersymbol interference (ISI) becomes a major consideration, as well as suspected causes such as reflections within the TWT. To experimentally investigate effects of the physical TWT on ISI would be prohibitively expensive, as it would require manufacturing numerous amplifiers, in addition to acquiring the required digital hardware. As an alternative, the time-domain TWT interaction model developed here provides the capability to establish a computational test bench where ISI or bit error rate can be simulated as a function of TWT operating parameters and component geometries. Intermodulation products, harmonic generation, and backward waves can also be monitored with the model for similar correlations. The advancements in computational capabilities and corresponding potential improvements in TWT performance may prove to be the enabling technologies for realizing unprecedented data rates for near real time transmission of the increasingly larger volumes of data demanded by planned commercial and Government satellite communications applications. This work is in support of the Cross Enterprise Technology Development Program in Headquarters' Advanced Technology & Mission Studies Division and the Air Force Office of Scientific Research Small Business Technology Transfer programs.

Kory, Carol L.↗
NASA NTRS2018

Stirling Convertor Controller Development at NASA Glenn Research Center

Over the past decade, NASA Glenn Research Center (GRC) has been supporting the development of Radioisotope Power Systems (RPS). NASA desires higher conversion efficiency RPS options that are reliable and robust with long life design. Dynamic conversion, such as Stirling and Brayton, offer the potential for higher conversion efficiencies but have yet to be demonstrated in a flight application. The RPS program sent out a solicitation to investigate options for dynamic conversion technologies. As a result of this solicitation, four dynamic power convertor (DPC) technologies were selected for design and fabrication of a prototype dynamic convertor. One lesson learned from the Advanced Stirling Radioisotope Generator (ASRG) project is that controller development should start early in the development of a dynamic convertor. As a result of this, NASA GRC has been utilizing hardware from past Stirling convertor projects including that of the ASRG to support controller development for the DPC's. NASA GRC has developed a strong knowledge base on both analog and digital Stirling dynamic power convertor controllers and will continue to expand and apply that knowledge to the four DPC's. Over the past 15 years, controllers were developed in-house at GRC, at Lockheed Martin Coherent Technologies (LMCT) and by the Johns Hopkins University/Applied Physics Laboratory (JHU/APL). Various generations of the controllers, have been developed as lessons were learned through various component and system level tests. Some of the tests performed were fault tolerance, qualification vibration level, electromagnetic interference, Radioisotope Power System Systems Integration (RSIL) tests, and extended operation. The fault tolerance test characterized the controller's ability to handle various fault conditions, including high or low bus power consumptions, total open load or short circuit, and replacing a failed controller card while the backup maintains control of the ASC. The vibration test confirms the controller's ability to control an ASC during launch. The EMI test characterized the AC and DC magnetic and electric fields emitted by the single ASC and if the controller has an impact on the radiated EMI. RSIL testing provided insight into the electrical interactions between the representative RPS, its associated control schemes, and realistic electric system loads. The extended operation test allows data to be collected over a period of thousands of hours to obtain long term performance data of the system. This paper describes the history of controller development at NASA GRC, tests performed on these controllers, and lessons learned.

Dugala, Gina M.↗
NASA NTRS2018

Development of an Optical Slice for an RF and Optical Software Defined Radio

A key component in the Integrated Radio and Optical Communications project at the National Aeronautics and Space Administration's (NASA) Glenn Research Center (GRC) is the radio frequency (RF) and optical software defined radio (SDR). A NASA RF SDR might consist of a general purpose processor to run the Space Telecommunications Radio System (STRS) Architecture for radio command and control, a reconfigurable signal processing device such as a field programmable gate array (FPGA) which houses the waveform, and a digital to analog converter (DAC) for transmitting data. Prior to development, SDR architecture trades on how to combine the RF and optical elements were studied. A modular architecture with physically separate RF and optical hardware slices was chosen and the optical slice of an SDR was designed and developed. The Harris AppSTARTM platform, which consists of an FPGA processing platform with a mezzanine card targeted for RF communications, was used as the base platform in prototyping the optical slice. A serially concatenated pulse position modulation (SCPPM) optical waveform was developed. The waveform follows the standard described in the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization Red Book. A custom optical mezzanine printed circuit board card was developed at NASA GRC for optical transmission. The optical mezzanine card replaces the DAC, which is used in the transmission of RF signals. This paper describes RF and optical SDR architecture trades, the Harris AppSTAR platform, the design of the SCPPM waveform, and the development of the optical mezzanine card.

Nappier, Jennifer M.↗
NASA NTRS1974

Quasi-perfect FIFO: Synchronous or asynchronous with application in controller design for the UNICON laser memory

The first-in-first-out memory buffer (FIFO), is an elastic digital memory whose main application is in data buffering between devices operating at different rates. Data written into the top is moved autonomously down toward the bottom of the FIFO to the lowest unoccupied location, and data read from the bottom of the FIFO will cause data from the top to move autonomously down toward the bottom. The FIFO is available in MOS LSI asynchronous form with data rate in the 1 MHz region. The FIFO described yields a simple high-speed iterative implementation, either synchronous of asynchronous. Because of this simple iterative structure, the FIFO is expandable in both number of words and bits per word, and it is attractive from the viewpoint of integrated-circuit production. For the synchronous FIFO, a model was built and successfully used in the controller for the UNICON laser memory. For the asynchronous FIFO, a model was built and also successfully used in a high-performance magnetic tape controller.

Lim, R. S.↗
NASA NTRS1986

Method and apparatus for operating on companded PCM voice data

The method and apparatus constructed in accordance with this invention permits a plurality of parties to speak to each other on a conference line with a minimum of interference. The apparatus digitizes audio signals. Each of the parties has an audio transmitter and receiver provided for transmitting and receiving audio signals. The audio signals are converted to a PCM companded eight-bit parallel signal followed by a conversion to a serial signal for transmitting to a remote location and then reconverting each of the companded signals to a first-eight-bit parallel signal. The eight-bit parallel signal is fed to one input of a pre-programmed ROM. This eight-bit signal provides one-half of a sixteen-bit address of a lookup ROM. The other half of the sixteen-bit ROM address is supplied by another suscriber over an identical circuit.

Byrne, F.↗
NASA NTRS1992

Real-time demonstration hardware for enhanced DPCM video compression algorithm

The lack of available wideband digital links as well as the complexity of implementation of bandwidth efficient digital video CODECs (encoder/decoder) has worked to keep the cost of digital television transmission too high to compete with analog methods. Terrestrial and satellite video service providers, however, are now recognizing the potential gains that digital video compression offers and are proposing to incorporate compression systems to increase the number of available program channels. NASA is similarly recognizing the benefits of and trend toward digital video compression techniques for transmission of high quality video from space and therefore, has developed a digital television bandwidth compression algorithm to process standard National Television Systems Committee (NTSC) composite color television signals. The algorithm is based on differential pulse code modulation (DPCM), but additionally utilizes a non-adaptive predictor, non-uniform quantizer and multilevel Huffman coder to reduce the data rate substantially below that achievable with straight DPCM. The non-adaptive predictor and multilevel Huffman coder combine to set this technique apart from other DPCM encoding algorithms. All processing is done on a intra-field basis to prevent motion degradation and minimize hardware complexity. Computer simulations have shown the algorithm will produce broadcast quality reconstructed video at an average transmission rate of 1.8 bits/pixel. Hardware implementation of the DPCM circuit, non-adaptive predictor and non-uniform quantizer has been completed, providing realtime demonstration of the image quality at full video rates. Video sampling/reconstruction circuits have also been constructed to accomplish the analog video processing necessary for the real-time demonstration. Performance results for the completed hardware compare favorably with simulation results. Hardware implementation of the multilevel Huffman encoder/decoder is currently under development along with implementation of a buffer control algorithm to accommodate the variable data rate output of the multilevel Huffman encoder. A video CODEC of this type could be used to compress NTSC color television signals where high quality reconstruction is desirable (e.g., Space Station video transmission, transmission direct-to-the-home via direct broadcast satellite systems or cable television distribution to system headends and direct-to-the-home).

Bizon, Thomas P.↗
NASA NTRS2018

Development of an Optical Slice for an RF and Optical Software Defined Radio

A key component in the Integrated Radio and Optical Communications project at the National Aeronautics and Space Administration's (NASA) Glenn Research Center (GRC) is the radio frequency (RF) and optical software defined radio (SDR). A NASA RF SDR might consist of a general purpose processor to run the Space Telecommunications Radio System (STRS) Architecture for radio command and control, a reconfigurable signal processing device such as a field programmable gate array (FPGA) which houses the waveform, and a digital to analog converter for (DAC) transmitting data. Prior to development, SDR architecture trades on how to combine the RF and optical elements were studied. A modular architecture with physically separate RF and optical hardware slices was chosen and the optical slice of an SDR was designed and developed. The Harris AppSTAR("TM") platform, which consists of an FPGA processing platform with a mezzanine card targeted for RF communications, was used as the base platform in prototyping the optical slice. A serially concatenated pulse position modulation (SCPPM) optical waveform was developed. The waveform follows the standard described in the Consultative Committee for Space Data Systems (CCSDS) Optical Communions Coding and Synchronization Red Book. A custom optical mezzanine printed circuit board card was developed at NASA GRC for optical transmission. The optical mezzanine card replaces the DAC, which is used in the transmission of RF signals. This paper describes RF and optical SDR architecture trades, the Harris AppSTAR("TM") platform, the design of the SCPPM waveform, and the development of the optical mezzanine card.

optical communications↗
NASA NTRS2004

Microscale Investigation of Thermo-Fluid Transport in the Transition FIL, Region of an Evaporating Capillary Meniscus Using a Microgravity Environment

In order to enhance the fundamental understanding of thin film evaporation and thereby improve the critical design concept for two-phase heat transfer devices, microscale heat and mass transport is to be investigated for the transition film region using state-of-the-art optical diagnostic techniques. By utilizing a microgravity environment, the length scales of the transition film region can be extended sufficiently, from submicron to micron, to probe and measure the microscale transport fields which are affected by intermolecular forces. Extension of the thin film dimensions under microgravity will be achieved by using a conical evaporator made of a thin silicon substrate under which concentric and individually controlled micro-heaters are vapor-deposited to maintain either a constant surface temperature or a controlled temperature variation. Local heat transfer rates, required to maintain the desired wall temperature boundary condition, will be measured and recorded by the concentric thermoresistance heaters controlled by a Wheatstone bridge circuit, The proposed experiment employs a novel technique to maintain a constant liquid volume and liquid pressure in the capillary region of the evaporating meniscus so as to maintain quasi-stationary conditions during measurements on the transition film region. Alternating use of Fizeau interferometry via white and monochromatic light sources will measure the thin film slope and thickness variation, respectively. Molecular Fluorescence Tracking Velocimetry (MFTV), utilizing caged fluorophores of approximately 10-nm in size as seeding particles, will be used to measure the velocity profiles in the thin film region. An optical sectioning technique using confocal microscopy will allow submicron depthwise resolution for the velocity measurements within the film for thicknesses on the order of a few microns. Digital analysis of the fluorescence image-displacement PDFs, as described in the main proposal, can further enhance the depthwise resolution.

Kihm, K. D.↗
NASA NTRS1985

Neighborhood comparison operator

Digital values in a moving window are compared by an operator having nine comparators connected to line buffers for receiving a succession of central pixels together with eight neighborhood pixels. A single bit of program control determines whether the neighborhood pixels are to be compared with the central pixel or a threshold value. The central pixel is always compared with the threshold. The omparator output plus 2 bits indicating odd-even pixel/line information about the central pixel addresses a lookup table to provide 14 bits of information, including 2 bits which control a selector to pass either the central pixel value, the other 12 bits of table information, or the bit-wise logical OR of all nine pixels through circuit that implements a very wide OR gate.

Gennery, D. B.↗
NASA NTRS2006

Power Actuation and Switching Module Test Results

The X2000 Power System Electronics (PSE) is a Jet Propulsion Laboratory (JPL) task to develop a new generation of power system building blocks for use on future deep-space missions. The effort includes the development of electronic components and modules that can be used as building blocks in the design of generic spacecraft power systems. All X2000 avionics components and modules are designed for use in centralized or distributed spacecraft architectures. The Power Actuation and Switching Module (PASM) has been developed under the X2000 program. This component enables a modular and scalable design approach for power switching applications, which can result in a wide variety of power switching architectures using this simple building block. The PASM is designed to provide most of the necessary power switching functions of spacecraft for various Deep Space missions including future missions to Mars, comets, Jupiter and its moons. It is fabricated using an ASIC process that is tolerant of high radiation. The development included two application specific integrated circuits (ASICs) and support circuitry all packaged using High Density Interconnect (HDI) technology. It can be operated in series or parallel with other PASMs. It can be used as a high-side or low-side switch and it can drive thruster valves, pyrotechnic devices such as NASA standard initiators, bus shunt resistors, and regular spacecraft component loads. Each PASM contains two independent switches with internal current limiting and over-current trip-off functions to protect the power subsystem from load faults. During turnon and turnoff each switch can limit the rate of current change (di/dt) to a value determined by the user. Three-way majority-voted On/Off commandability and full switch status telemetry (both analog and digital) are built into the module. This paper is a follow up to the one presented at he IECEC 2004 conference that will include the lessons learned and test results from the development.

X2000↗
NASA NTRS2011

Science Enabling ASICs and FEEs for the JUICE and JEO Missions

A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

Paschalidis, Nicholas↗
NASA NTRS1983

Complementary code and digital filtering for detection of weak VHF radar signals from the mesoscale

The SOUSY-VHF-Radar operates at a frequency of 53.5 MHz in a valley in the Harz mountains, Germany, 90 km from Hanover. The radar controller, which is programmed by a 16-bit computer holds 1024 program steps in core and controls, via 8 channels, the whole radar system: in particular the master oscillator, the transmitter, the transmit-receive-switch, the receiver, the analog to digital converter, and the hardware adder. The high-sensitivity receiver has a dynamic range of 70 dB and a video bandwidth of 1 MHz. Phase coding schemes are applied, in particular for investigations at mesospheric heights, in order to carry out measurements with the maximum duty cycle and the maximum height resolution. The computer takes the data from the adder to store it in magnetic tape or disc. The radar controller is programmed by the computer using simple FORTRAN IV statements. After the program has been loaded and the computer has started the radar controller, it runs automatically, stopping at the program end. In case of errors or failures occurring during the radar operation, the radar controller is shut off caused either by a safety circuit or by a power failure circuit or by a parity check system.

Schmidt, G.↗