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At least 1,117 records · Page 62

Are Lock-Free Concurrent Algorithms Practically Wait-Free?

Lock-free concurrent algorithms guarantee that some concurrent operation will always make progress in a finite number of steps. Yet programmers prefer to treat concurrent code as if it were wait-free, guaranteeing that all operations always make progress. Unfortunately, designing wait-free algorithms is generally a very complex task, and the resulting algorithms are not always efficient. Although obtaining efficient wait-free algorithms has been a long-time goal for the theory community, most nonblocking commercial code is only lock-free. This article suggests a simple solution to this problem. We show that for a large class of lock-free algorithms, under scheduling conditions that approximate those found in commercial hardware architectures, lock-free algorithms behave as if they are wait-free. In other words, programmers can continue to design simple lock-free algorithms instead of complex wait-free ones, and in practice, they will get wait-free progress. Our main contribution is a new way of analyzing a general class of lock-free algorithms under a stochastic scheduler. Our analysis relates the individual performance of processes to the global performance of the system using Markov chain lifting between a complex per-process chain and a simpler system progress chain. We show that lock-free algorithms are not only wait-free with probability 1 but that in fact a general subset of lock-free algorithms can be closely bounded in terms of the average number of steps required until an operation completes. Here, to the best of our knowledge, this is the first attempt to analyze progress conditions, typically stated in relation to a worst-case adversary, in a stochastic model capturing their expected asymptotic behavior.

97 MATHEMATICS AND COMPUTING↗

PapyrusKV: a high-performance parallel key-value store for distributed NVM architectures

This paper introduces PapyrusKV, a parallel embedded key-value store (KVS) for distributed high-performance computing (HPC) architectures that offer potentially massive pools of nonvolatile memory (NVM). PapyrusKV stores keys with their values in arbitrary byte arrays across multiple NVMs in a distributed system. PapyrusKV provides standard KVS operations such as put, get, and delete. More importantly, PapyrusKV provides advanced features for HPC such as dynamic consistency control, zero-copy workflow, and asynchronous checkpoint/restart. Beyond filesystems, PapyrusKV provides HPC programmers with a high-level interface to exploit distributed NVM in the system, and it transparently organizes data to achieve high performance. Also, it allows HPC applications to specialize PapyrusKV to meet their specific requirements. We empirically evaluate PapyrusKV on three HPC systems with real NVM devices: OLCF's Summitdev, TACC's Stampede, and NERSC's Cori. Our results show that PapyrusKV can offer high performance, scalability, and portability across these various distributed NVM architectures.

97 MATHEMATICS AND COMPUTING↗

Benchmarking and Evaluating Unified Memory for OpenMP GPU Offloading

Here, the latest OpenMP standard offers automatic device offloading capabilities which facilitate GPU programming. Despite this, there remain many challenges. One of these is the unified memory feature introduced in recent GPUs. GPUs in current and future HPC systems have enhanced support for unified memory space. In such systems, CPU and GPU can access each other's memory transparently, that is, the data movement is managed automatically by the underlying system software and hardware. Memory over subscription is also possible in these systems. However, there is a significant lack of knowledge about how this mechanism will perform, and how programmers should use it. We have modified several benchmarks codes, in the Rodinia benchmark suite, to study the behavior of OpenMP accelerator extensions and have used them to explore the impact of unified memory in an OpenMP context. We moreover modified the open source LLVM compiler to allow OpenMP programs to exploit unified memory. The results of our evaluation reveal that, while the performance of unified memory is comparable with that of normal GPU offloading for benchmarks with little data reuse, it suffers from significant overhead when GPU memory is over subcribed for benchmarks with large amount of data reuse. Based on these results, we provide several guidelines for programmers to achieve better performance with unified memory.

97 MATHEMATICS AND COMPUTING↗

FLASH: FPGA-Accelerated Smart Switches with GCN Case Study

Some communication switches, e.g., the Mellanox SHArP and those in the IBM BlueGene clusters, are augmented to process packets at the application level with fixed-function collectives. This approach, however, lacks flexibility, which limits their applicability in diverse and dynamic workloads. Recently, a new type of programmable packet processor, which uses high-level languages, e.g., P4, has emerged as possible candidates. P4-based switches, however, fall short in certain applications, including machine learning, where capabilities not currently supported by P4 are needed. These include more complex calculation, such as sparse computation and fused multiply-accumulate, data-intensive floating point operations, data reuse, and significant memory. The problem addressed here is that such a switch augmentation needs to support: a large amount of state, significant flexible compute capability, and ease of programming, all while maintaining full functionality, including ensuring high throughput, and demonstrating utility. In this work, we propose a programmable look-aside-type accelerator that can be embedded into, or attached to, existing communication switch pipelines and that is capable of processing packets at line-rate. The proposed in-switch accelerator is based on mixing an ISA (subset of RISC-V instructions) with dataflow graphs (found in CGRAs). To augment performance, vector instructions are also supported. To facilitate usability, we have developed a complete toolchain to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator. While this approach is flexible enough to support various workloads, in this paper, we consider Graph Convolutional Networks (GCNs) as a case study. Experimental results show that this approach considerably improves the performance of distributed GCN applications.

Haghi, Pouya↗

Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals

Many applications are designed to perform traversals ontree-likedata structures. Fusing and parallelizing these traversals enhance the performance of applications. Fusing multiple traversals improves the locality of the application. The runtime of an application can be significantly reduced by extracting parallelism and utilizing multi-threading. Prior frameworks have tried to fuse and parallelize tree traversals using coarse-grained approaches, leading to missed fine-grained opportunities for improving performance. Other frameworks have successfully supported fine-grained fusion on heterogeneous tree types but fall short regarding parallelization. We introduce a new frameworkOrchardbuilt on top ofGrafter.Orchard’s novelty lies in allowing the programmer to transform tree traversal applications by automatically applyingfine-grainedfusion and extractingheterogeneousparallelism.Orchardallows the programmer to write general tree traversal applications in a simple and elegant embedded Domain-Specific Language (eDSL). We show that the combination of fine-grained fusion and heterogeneous parallelism performs better than each alone when the conditions are met.

Computer Science↗

Complex Parsing for In-Network Acceleration of High-Energy Physics Experiments

This paper describes a novel application and evaluation of programmable networking in High-Energy Physics (HEP): a complete parser for the custom packet format used by Fermilab’s DUNE experiment. Notably, this parser is implemented on a Tofino programmable network switch and evaluated on the FABRIC testbed by using network traffic generated by the ICEBERG DUNE prototype. The parsed network traffic consists of Jumbo Ethernet frames that contain digitizations of sensor readings from ICEBERG’s detector.This work is an early investigation into providing in-network processing support for HEP experiments. The paper describes DUNE’s custom packet format, the challenges encountered when implementing a parser for that format, and an exploration of the techniques that are needed to overcome those challenges. We identify performance bottlenecks and discuss directions for future research.

Sagstad, Bjoern [IIT, Chicago] (ORCID:000900033610↗

Steam Oxidation of Fossil Power Plant Materials. Collaborative Research to Enable Advanced Steam Power Cycles

Research into improved materials systems and associated manufacturing and reliability issues is a major part of initiatives to produce cleaner and cheaper energy systems in the UK and the USA. Under the auspices of a Memorandum of Understanding on Energy R&D, a work programme concerned with steam oxidation has been conducted. The focus was on the generation of definitive information regarding the oxidation behaviour in steam of current and developmental ferritic steels, austenitic steels, and nickel-based alloys required to enable advanced steam power cycles. The results were intended to provide a basis for quantifying the rate of metal loss expected under advanced steam cycle conditions, as well as understanding of the evolution of oxide scale morphologies with time and temperature to identify features that could influence scale exfoliation characteristics. This understanding and acquired data were used to develop and validate models of oxide growth and loss by exfoliation. This paper provides an overview of the activity and highlights a selection of the results coming from the programme.

20 FOSSIL-FUELED POWER PLANTS↗

The RNA-binding protein ELAV regulates Hox RNA processing, expression and function within the Drosophila nervous system

The regulated head-to-tail expression of Hox genes provides a coordinate system for the activation of specific programmes of cell differentiation according to axial level. Recent work indicates that Hox expression can be regulated via RNA processing but the underlying mechanisms and biological significance of this form of regulation remain poorly understood. Here we explore these issues within the developing Drosophila central nervous system (CNS). We show that the pan-neural RNA-binding protein (RBP) ELAV (Hu antigen) regulates the RNA processing patterns of the Hox gene Ultrabithorax (Ubx) within the embryonic CNS. Using a combination of biochemical, genetic and imaging approaches we demonstrate that ELAV binds to discrete elements within Ubx RNAs and that its genetic removal reduces Ubx protein expression in the CNS leading to the respecification of cellular subroutines under Ubx control, thus defining for the first time a specific cellular role of ELAV within the developing CNS. Artificial provision of ELAV in glial cells (a cell type that lacks ELAV) promotes Ubx expression, suggesting that ELAV-dependent regulation might contribute to cell type-specific Hox expression patterns within the CNS. Finally, we note that expression of abdominal A and Abdominal B is reduced in elav mutant embryos, whereas other Hox genes (Antennapedia) are not affected. Based on these results and the evolutionary conservation of ELAV and Hox genes we propose that the modulation of Hox RNA processing by ELAV serves to adapt the morphogenesis of the CNS to axial level by regulating Hox expression and consequently activating local programmes of neural differentiation.

59 BASIC BIOLOGICAL SCIENCES↗

Progresses in tritium accident modelling in the frame of IAEA EMRAS II

The assessment of the environmental impact of tritium release from nuclear facilities is a topic of interest in many countries. In the IAEA's Environmental Modelling for Radiation Safety (EMRAS I) programme, progresses for routine releases were done and in the EMRAS II programme a dedicated working group (WG 7 - Tritium Accidents) focused on the potential accidental releases (liquid and atmospheric pathways). The progresses achieved in WG 7 were included in a complex report - a technical document of IAEA covering both liquid and atmospheric accidental release consequences. A brief description of the progresses achieved in the frame of EMRAS II WG 7 is presented. Important results have been obtained concerning washout rate, the deposition on the soil of HTO and HT, the HTO uptake by leaves and the subsequent conversion to OBT (organically bound tritium) during daylight. Further needs of the processes understanding and the experimental efforts are emphasised.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

Post-processing of phase change material in a zero-change commercial silicon photonic process

Integration of phase change material (PCM) with photonic integrated circuits can transform large-scale photonic systems by providing non-volatile control over phase and amplitude. The next generation of commercial silicon photonic processes can benefit from the addition of PCM to enable ultra-low power, highly reconfigurable, and compact photonic integrated circuits for large-scale applications. Despite all the advantages of PCM-based photonics, today’s commercial foundries do not provide them in their silicon photonic processes yet. We demonstrate the first-ever electrically programmable PCM device that is monolithically post-processed in a commercial foundry silicon photonics process using a few fabrication steps and coarse-resolution photolithography. These devices achieved 1.4 dB/μm of amplitude switching contrast using a thin layer of 12.5 nm GeSbTe in this work. We have also characterized the reconfiguration speed as well as repeatability of these devices over 20,000 switching cycles. Our solution enables non-volatile photonic VLSI systems that can be fabricated at low cost and high reliability in a commercial foundry process, paving the way for the development of non-volatile programmable photonic integrated circuits for a variety of emerging applications.

Optics↗

Rapidly tunable ultrabroadband flying focus using adaptive optics and an axiparabola

A programmable ultrabroadband flying focus was produced using adaptive optics and an axiparabola with a continuous wave superluminescent diode. A deformable mirror and spatial light modulator were used to add a programmable amount of radial group delay, and an axiparabola was used to create an extended focus by imparting spherical aberration. Three different flying focus trajectories were measured using spectral interferometry, two with uniform velocity and one with an accelerating velocity. Here, the temporal response function width of the flying focus optics alone was calculated to be 52 ± 6 fs, and the focal spot size was measured to be (1.2 ± 0.1) × larger than the diffraction-limited spot size through the extended focus.

Markland, H. S. [University of Rochester, NY (Unit↗

A RESTful API for accessing microbial community data for MG-RAST

Metagenomic sequencing has produced significant amounts of data in recent years. For example, as of summer 2013, MGRAST has been used to annotate over 110,000 data sets totaling over 43 Terabases. With metagenomic sequencing finding even wider adoption in the scientific community, the existing web-based analysis tools and infrastructure in MG-RAST provide limited capability for data retrieval and analysis, such as comparative analysis between multiple data sets. Moreover, although the system provides many analysis tools, it is not comprehensive. By opening MG-RAST up via a web services API (application programmers interface) we have greatly expanded access to MG-RAST data, as well as provided a mechanism for the use of third-party analysis tools with MG-RAST data. This RESTful API makes all data and data objects created by the MG-RAST pipeline accessible as JSON objects. As part of the DOE Systems Biology Knowledgebase project (KBase, http:// kbase.us) we have implemented a web services API for MG-RAST. This API complements the existing MG-RAST web interface and constitutes the basis of KBase’s microbial community capabilities. In addition, the API exposes a comprehensive collection of data to programmers. This API, which uses a RESTful (Representational State Transfer) implementation, is compatible with most programming environments and should be easy to use for end users and third parties. It provides comprehensive access to sequence data, quality control results, annotations, and many other data types. Where feasible, we have used standards to expose data and metadata. Code examples are provided in a number of languages both to show the versatility of the API and to provide a starting point for users. We present an API that exposes the data in MG-RAST for consumption by our users, greatly enhancing the utility of the MG-RAST service.

59 BASIC BIOLOGICAL SCIENCES↗

Probing fractional statistics in quantum simulators of spin liquid Hamiltonians

Recent advances in programmable quantum devices brought to the fore the intriguing possibility of using them to realise and investigate topological quantum spin liquid phases. This new and exciting direction brings about important research questions on how to probe and determine the presence of such exotic, highly entangled phases in a noisy quantum environment. One of the most promising tools is investigating the behaviour of the topological excitations, and in particular their fractional statistics. In this work we put forward a generic route to achieve this, and we illustrate it in the specific case of \mathbb{Z}_2 ℤ 2 topological spin liquids implemented with the aid of combinatorial gauge symmetry. We design a convenient architecture to study signatures of fractional statistics via quasiparticle interferometry, and we assess its robustness to diagonal and off-diagonal disorder, as well as to dephasing - effects that are generally pervasive in current quantum programmable devices. Interestingly, when turned on its head, our scheme provides a remarkably clear test of the “quantumness” of these devices, with robust signatures that crucially hinge on quantum coherence and quantum interference effects, and cannot be mimicked by classical stochastic processes.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Final Report

The purpose of this project was to develop tools and techniques to improve the ability of computational scientists to investigate and correct problems (bugs) in their programs. Specifically, the University of Maryland component of this project focused on the problems associated with the finite number of bits available in a computer to represent numeric values. In large scale scientific computation, numbers are frequently added to and multiplied with each other billions of times. Thus even small errors due to the representation of numbers can accumulate into big errors. However, using too many bits to represent a number results in additional computation, memory, and energy costs. Thus it is critical to find the right size for numbers. This project focused on several aspects of this general problem. First, we developed a tool to look for cancelations, the catastrophic loss of precision in numbers due to the addition of two numbers whose actual values are close to each other, but whose representation in a computer is identical or nearly so. Second, we developed a suite of tools to allow programmers to identify exactly how much precision is required for each operation in their program. This tool allows programmers to both verify that enough precision is available, but more importantly find cases where extra precision could be eliminated to allow the program to use less memory, computer time, or energy. These tools use advanced binary modification techniques to allow the analysis of actual optimized code. The system, called Craft, has been applied to a number of benchmarks and real applications.

97 MATHEMATICS AND COMPUTING↗

CCG-Flasks Instrument Handbook

Surface-based sampling Samples are collected from the one of the two 60m inlet in the PGS shed. A site technician triggers sampling, usually at 2pm local time, every Thursday. Eacl flask (2.5liters) is sampled for about 2 minutes and pressurized to 40 PSI. This system automatically purges the flasks, dries the air sample, and fills the flasks. Aircraft-based sampling Samples are collected from the community inlet for as many as twelve elevations. The pilot triggers sampling when location and latitude have been reached. Each flask (0.75 liters) is sampled for about 2 minutes and pressurized to 40 PSI. The sampler has two components: (1) a rack mounted programmable compressor package (PCP, see picture below) and (2) a programmable flask package (PFP). Prior each flight, the pilot connects a new PFP to the PCP. An automatic test is then performed to check for leaks. After each flight the PFP is sent back to the laboratory for analysis of trace gases.

47 OTHER INSTRUMENTATION↗

US Global Change Research Program Distributed Cost Budget Interagency Funds Transfer from DOE to NSF

These funds were transferred from DOE to NSF as DOE's contribution to the U.S. Global Change Research Program in support of 4 internationalnactivities/programs as approved by the U.S. Global Change Research Program on 14 March 2014. The programs are the International Geosphere-Biosphere Programme, the DIVERSITAS programme, and the World Climate Research Program. All program awards ended as of 09-23-2015.

99 GENERAL AND MISCELLANEOUS↗

Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

97 MATHEMATICS AND COMPUTING↗

Domain Specific Language Support for Exascale

A multi-institutional project known as D-TEC (short for “Domain- specific Technology for Exascale Computing”) set out to explore technologies to support the construction of Domain Specific Languages (DSLs) to map application programs to exascale architectures. DSLs employ automated code transformation to shift the burden of delivering portable performance from application programmers to compilers. Two chief properties contribute: DSLs permit expression at a high level of abstraction so that a programmer’s intent is clear to a compiler and DSL implementations encapsulate human domain-specific optimization knowledge so that a compiler can be smart enough to achieve good results on specific hardware. Domain specificity is what makes these properties possible in a programming language. If leveraging domain specificity is the key to keep exascale software tractable, a corollary is that many different DSLs will be needed to encompass the full range of exascale computing applications; moreover, a single application may well need to use several different DSLs in conjunction. As a result, developing a general toolkit for building domain-specific languages was a key goal for the D-TEC project. Different aspects of the D-TEC research portfolio were the focus of work at each of the partner institutions in the multi-institutional project. D-TEC research and development work at Rice University focused on on three principal topics: understanding how to automate the tuning of code for complex architectures, research and development of the Rosebud DSL engine, and compiler technology to support complex execution platforms. This report provides a summary of the research and development work on the D-TEC project at Rice University.

97 MATHEMATICS AND COMPUTING↗