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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,117 records · Page 62
All sourcesNASA NTRSDOE OSTI
NASA NTRS1996

Advanced Technology: It's Available at JPL

Non-NASA activities at JPL are the province of the JPL Technology and Applications Programs Directorate, and include working relationships with industry, academia, and other government agencies. Within this Directorate, the JPL Undersea Technology Program endeavors to apply and transfer these capabilities to the area of underwater research and operations. Of particular interest may be a Reversed Electron Attachment Detector (READ). It is a man-portable device capabable of unambiguous detection of unique chemical signatures associated with mines. In addition, there are other JPL technologies which merit investigation for marine applications.

microelectronics undersea technology mines chemica↗
NASA NTRS1995

JPL CMOS Active Pixel Sensor Technology

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Space Microelectronics Image Sensors APS Digital I↗
NASA NTRS1995

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Space Microelectronics Image Sensors APS Digital I↗
NASA NTRS1995

CMOS Image Sensors: Electronic Camera On A Chip

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Space Microelectronics Image Sensors APS Digital I↗
NASA NTRS1995

Low Power Camera-on-a-Chip Using CMOS Active Pixel Sensor Technology

A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.

Space Microelectronics Image Sensors APS Digital I↗
NASA NTRS2003

Endurance cycling results in extreme environments

A new test bed for life testing flash memories in extreme environments is introducted. the test bed is based on a state-of-the-art development board. Since space applications often desire state-of-the-art devices, such a basis seems appropriate. Comparison of this tester to other such systems, including those with data presented here in the past is made. Limitations of different testers for varying applications are discussed. Recently developed data, using this test bed is also presented.

microelectronics↗
NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗
NASA NTRS2012

High Performance Fuel Cell and Electrolyzer Membrane Electrode Assemblies (MEAs) for Space Energy Storage Systems

Regenerative fuel cells provide a pathway to energy storage system development that are game changers for NASA missions. The fuel cell/ electrolysis MEA performance requirements 0.92 V/ 1.44 V at 200 mA/cm2 can be met. Fuel Cell MEAs have been incorporated into advanced NFT stacks. Electrolyzer stack development in progress. Fuel Cell MEA performance is a strong function of membrane selection, membrane selection will be driven by durability requirements. Electrolyzer MEA performance is catalysts driven, catalyst selection will be driven by durability requirements. Round Trip Efficiency, based on a cell performance, is approximately 65%.

Plastic Encapsulated Microelectronics (PEM)↗
NASA NTRS2014

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Microelectronics↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗