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All sourcesNASA NTRSDOE OSTI
NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗
NASA NTRS2011

Thermal Properties of Microstrain Gauges Used for Protection of Lithium-Ion Cells of Different Designs

The purpose of this innovation is to use microstrain gauges to monitor minute changes in temperature along with material properties of the metal cans and pouches used in the construction of lithium-ion cells. The sensitivity of the microstrain gauges to extremely small changes in temperatures internal to the cells makes them a valuable asset in controlling the hazards in lithium-ion cells. The test program on lithium-ion cells included various cell configurations, including the pouch type configurations. The thermal properties of microstrain gauges have been found to contribute significantly as safety monitors in lithium-ion cells that are designed even with hard metal cases. Although the metal cans do not undergo changes in material property, even under worst-case unsafe conditions, the small changes in thermal properties observed during charge and discharge of the cell provide an observable change in resistance of the strain gauge. Under abusive or unsafe conditions, the change in the resistance is large. This large change is observed as a significant change in slope, and this can be used to prevent cells from going into a thermal runaway condition. For flexible metal cans or pouch-type lithium-ion cells, combinations of changes in material properties along with thermal changes can be used as an indication for the initiation of an unsafe condition. Lithium-ion cells have a very high energy density, no memory effect, and almost 100-percent efficiency of charge and discharge. However, due to the presence of a flammable electrolyte, along with the very high energy density and the capability of releasing oxygen from the cathode, these cells can go into a hazardous condition of venting, fire, and thermal runaway. Commercial lithium-ion cells have current and voltage monitoring devices that are used to control the charge and discharge of the batteries. Some lithium-ion cells have internal protective devices, but when used in multi-cell configurations, these protective devices either do not protect or are themselves a hazard to the cell due to their limitations. These devices do not help in cases where the cells develop high impedance that suddenly causes them to go into a thermal runaway condition. Temperature monitoring typically helps with tracking the performance of a battery. But normal thermistors or thermal sensors do not provide the accuracy needed for this and cannot track a change in internal cell temperatures until it is too late to stop a thermal runaway.

Jeevarajan, Judith↗
DOE OSTI2023

Predicting Kyasanur forest disease in resource-limited settings using event-based surveillance and transfer learning

In recent years, the reports of Kyasanur forest disease (KFD) breaking endemic barriers by spreading to new regions and crossing state boundaries is alarming. Effective disease surveillance and reporting systems are lacking for this emerging zoonosis, hence hindering control and prevention efforts. We compared time-series models using weather data with and without Event-Based Surveillance (EBS) information, i.e., news media reports and internet search trends, to predict monthly KFD cases in humans. We fitted Extreme Gradient Boosting (XGB) and Long Short-Term Memory models at the national and regional levels. We utilized the rich epidemiological data from endemic regions by applying Transfer Learning (TL) techniques to predict KFD cases in new outbreak regions where disease surveillance information was scarce. Overall, the inclusion of EBS data, in addition to the weather data, substantially increased the prediction performance across all models. The XGB method produced the best predictions at the national and regional levels. The TL techniques outperformed baseline models in predicting KFD in new outbreak regions. Novel sources of data and advanced machine-learning approaches, e.g., EBS and TL, show great potential towards increasing disease prediction capabilities in data-scarce scenarios and/or resource-limited settings, for better-informed decisions in the face of emerging zoonotic threats.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2023

Vibrational heat-bath configuration interaction with semistochastic perturbation theory using harmonic oscillator or VSCF modals

Vibrational heat-bath configuration interaction (VHCI)—a selected configuration interaction technique for vibrational structure theory—has recently been developed in two independent works [J. H. Fetherolf and T. C. Berkelbach, J. Chem. Phys. 154, 074104 (2021); A. U. Bhatty and K. R. Brorsen, Mol. Phys. 119, e1936250 (2021)], where it was shown to provide accuracy on par with the most accurate vibrational structure methods with a low computational cost. Here, we eliminate the memory bottleneck of the second-order perturbation theory correction using the same (semi)stochastic approach developed previously for electronic structure theory. This allows us to treat, in an unbiased manner, much larger perturbative spaces, which are necessary for high accuracy in large systems. Stochastic errors are easily controlled to be less than 1 cm−1. We also report two other developments: (i) we propose a new heat-bath criterion and an associated exact implicit sorting algorithm for potential energy surfaces expressible as a sum of products of one-dimensional potentials; (ii) we formulate VHCI to use a vibrational self-consistent field (VSCF) reference, as opposed to the harmonic oscillator reference configuration used in previous reports. Our tests are done with quartic and sextic force fields, for which we find that with VSCF, the minor improvements to accuracy are outweighed by the higher computational cost associated the matrix element evaluations. We expect VSCF-based VHCI to be important for more general potential representations, for which the harmonic oscillator basis function integrals are no longer analytic.

Chemistry↗
DOE OSTI2021

Nanosecond Gated CMOS Camera (NSGCC) ICD (Rev. 2.1)

The Ultra-Fast X-ray Imager (UXI) program is an ongoing effort at Sandia National Laboratories to create high speed, multi-frame, time-gated Read Out Integrated Circuits (ROICs), and a corresponding suite of photodetectors to image a wide variety of High Energy Density (HED) physics experiments on both Sandia’s Z-Machine and LLNL’s National Ignition Facility (NIF). Several cameras have been designed over the length of the program; one of the most recent is the Icarus, which is an improvement on past imagers (Furi and Hippogriff). A second sensor that can be connected is the Daedalus sensor. The Icarus is a 1024 × 512-pixel array with either 25 μm or 8 µm spatial resolution containing four frames of storage per pixel and has improved timing generation and distribution components while achieved 2 ns time gating. The Daedalus sensor is also a 1024 x 512-pixel array with 25 µm special resolution containing three frames of storage per pixel and has an increased set of features for a wider variety of applications from interlacing of rows in each frame to configurability of all shutters. See Section 14 for details regarding the Icarus implementation of the firmware and Section 15 for details regarding the Daedalus implementation. Due to the unique test environments UXI sensors are targeted for, full custom hardware was required to physically mount an Icarus or Daedalus sensor, manage its various functions, and read out pixel data for transfer to a host computer. Beyond experimental functionality, the hardware also needed to accommodate sensor characterization requirements. Lawrence Livermore National Laboratory’s ‘Version 4.0 Board’ was the result of these efforts. It mounts all the components required to fully utilize the Icarus and Daedalus sensors including analog to digital converters to convert pixel data and various system voltages to digital form for readout and analysis, DAC channels for remote configuration of critical bias voltages, static random-access memories to buffer pixel data, RS422 and Gigabit Ethernet communications for remote access, and an FPGA to tie these components together. This document describes the FPGA electrical interfaces in detail to allow the reader a greater understanding of the device, and to facilitate implementation of custom software to control and manage it. The Version 4.0 Board is a continuation of the Nano-second Gated CMOS hardware design that retains much of the functionality of the Version 1.0 Board while adding features including a DAC instead of digital potentiometers, as well as sensors for pressure and radiation. The Version 4.0 board is intended for applications requiring tight form-factor enclosures. It is composed of two stacking boards; one holds the FPGA and regulators to power the various components of the board while the other contains the mating connector to the sensor, image-readoff ADCs, the DAC, and other components.

42 ENGINEERING↗
NASA NTRS1982

Computer program for post-flight evaluation of a launch vehicle upper-stage on-off reaction control system

This report describes a FORTRAN IV coded computer program for post-flight evaluation of a launch vehicle upper stage on-off reaction control system. Aerodynamic and thrust misalignment disturbances are computed as well as the total disturbing moments in pitch, yaw, and roll. Effective thrust misalignment angle time histories of the rocket booster motor are calculated. Disturbing moments are integrated and used to estimate the required control system total inpulse. Effective control system specific inpulse is computed for the boost and coast phases using measured control fuel useage. This method has been used for more than fifteen years for analyzing the NASA Scout launch vehicle second and third-stage reaction control system performance. The computer program is set up in FORTRAN IV for a CDC CYBER 175 system. With slight modification it can be used on other machines having a FORTRAN compiler. The program has optional CALCOMP plotting output. With this option the program requires 19K words of memory and has 786 cards. Running time on a CDC CYBER 175 system is less than three (3) seconds for a typical problem.

Knauber, R. N.↗
NASA NTRS1987

A generic applications subroutine library for the MPP

A new methodology to increase the utility of the Massively Parallel Processor (MPP) was developed, and is presented as an addition to the current methods of using the MPP. This methodology provides for the development of an MPP side abstraction layer that is callable from any host side high level language. Routines in the abstraction layer have the option of using a powerful software tool for accessing the stager as virtual memory. An additional abstraction layer that allows for remote access to the MPP via DECnet is discussed. This integrated approach to programming the MPP is a valuable tool for the implementation of interactive user driver systems that require the computational capabilities of the MPP as well as a controlled user view. It is expected that this methodology will be used to integrate the MPP into many such systems, and thus promote greater use of the MPP by scientific researchers who are accustomed to user friendly environments.

Gough, Michael L.↗
NASA NTRS2017

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Al Hassan, Mohammad↗
NASA NTRS2018

Effect of Thin-Film Adhesives on Mode II Interlaminar Fracture Toughness in Carbon Fiber Composites with Shape Memory Alloy Inserts

A single sheet of nickel-titanium (NiTi) shape memory alloy (SMA) was introduced within an IM7/8552 polymer matrix composite (PMC) panel in conjunction with multiple thin film adhesives to promote the interfacial bond strength between the SMA and PMC. End notched flexure (ENF) testing was performed in accordance to ASTM D7905 method for evaluation of mode II interlaminar fracture toughness (GIIC) of unidirectional fiber-reinforced polymer matrix composites. Acoustic emissions (AE) were monitored during testing with two acoustic sensors attached to the specimens. The composite panels were subjected to C-scan before testing, and examined using optical and scanning electron microscopy techniques after part failure. GIIC values for the control composite samples were found to be higher than those of samples with embedded SMA sheets. The presence of adhesives bonded to SMA sheets further diminished the GIIC values. AE values revealed poor bonding of the panels, with little to no signals during testing.

End Notched Flexure↗
DOE OSTI2023

Suppressing Structural Relaxation in Nanoscale Antimony to Enable Ultralow‐Drift Phase‐Change Memory Applications

Abstract Phase‐change random‐access memory (PCRAM) devices suffer from pronounced resistance drift originating from considerable structural relaxation of phase‐change materials (PCMs), which hinders current developments of high‐capacity memory and high‐parallelism computing that both need reliable multibit programming. This work realizes that compositional simplification and geometrical miniaturization of traditional GeSbTe‐like PCMs are feasible routes to suppress relaxation. While to date, the aging mechanisms of the simplest PCM, Sb, at nanoscale, have not yet been unveiled. Here, this work demonstrates that in an optimal thickness of only 4 nm, the thin Sb film can enable a precise multilevel programming with ultralow resistance drift coefficients, in a regime of ≈10 −4 –10 −3 . This advancement is mainly owed to the slightly changed Peierls distortion in Sb and the less‐distorted octahedral‐like atomic configurations across the Sb/SiO 2 interfaces. This work highlights a new indispensable approach, interfacial regulation of nanoscale PCMs, for pursuing ultimately reliable resistance control in aggressively‐miniaturized PCRAM devices, to boost the storage and computing efficiencies substantially.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1992

Diagnosis of NMOS DRAM functional performance as affected by a picosecond dye laser

A picosec pulsed dye laser beam was at selected wavelengths successfully used to simulate heavy-ion single-event effects (SEEs) in negative channel NMOS DRAMs. A DRAM was used to develop the test technique because bit-mapping capability and previous heavy-ion upset data were available. The present analysis is the first to establish such a correlation between laser and heavy-ion data for devices, such as the NMOS DRAM, where charge collection is dominated by long-range diffusion, which is controlled by carrier density at remote distances from a depletion region. In the latter case, penetration depth is an important parameter and is included in the present analysis. A single-pulse picosecond dye laser beam (1.5 microns diameter) focused onto a single cell component can upset a single memory cell; clusters of memory cell upsets (multiple errors) were observed when the laser energy was increased above the threshold energy. The multiple errors were analyzed as a function of the bias voltage and total energy of a single pulse. A diffusion model to distinguish the multiple upsets from the laser-induced charge agreed well with previously reported heavy ion data.

Kim, Q.↗
NASA NTRS1994

FFT Computation with Systolic Arrays, A New Architecture

The use of the Cooley-Tukey algorithm for computing the l-d FFT lends itself to a particular matrix factorization which suggests direct implementation by linearly-connected systolic arrays. Here we present a new systolic architecture that embodies this algorithm. This implementation requires a smaller number of processors and a smaller number of memory cells than other recent implementations, as well as having all the advantages of systolic arrays. For the implementation of the decimation-in-frequency case, word-serial data input allows continuous real-time operation without the need of a serial-to-parallel conversion device. No control or data stream switching is necessary. Computer simulation of this architecture was done in the context of a 1024 point DFT with a fixed point processor, and CMOS processor implementation has started.

Boriakoff, Valentin↗
NASA NTRS2019

Integrated Research Plan to Assess the Combined Effects of Space Radiation, Altered Gravity, and Isolation and Confinement on Crew Health and Performance: Problem Statement

Future crewed exploration missions to Mars could last up to three years and will expose astronauts to unprecedented environmental challenges. Challenges to the nervous system during these missions will include factors of: space radiation that can damage sensitive neurons in the central nervous system (CNS); isolation and confinement can affect cognition and behavior; and altered gravity that will change the astronauts’ perception of their environment and their spatial orientation, and will affect their coordination, balance, and locomotion. In the past, effects of spaceflight stressors have been characterized individually. However, long-term, simultaneous exposure to multiple stressors will produce a range of interrelated behavioral and biological effects that have the potential to adversely affect operationally relevant crew performance. These complex environmental challenges might interact synergistically and increase the overall risk to the health and performance of the astronaut. Therefore, NASA’s Human Research Program (HRP) has directed an integrated approach to characterize and mitigate the risk to the CNS from simultaneous exposure to these multiple spaceflight factors. The proposed research strategy focuses on systematically evaluating the relationships among three existing research risks associated with spaceflight: Risk of Acute (In-flight) and Late Central Nervous System Effects from Radiation (CNS), Risk of Adverse Cognitive or Behavioral Conditions and Psychiatric Disorders (BMed), and Risk of Impaired Control of Spacecraft/Associated Systems and Decreased Mobility Due to Vestibular/Sensorimotor Alterations Associated with Spaceflight (SM). NASA’s HRP approach is intended to identify the magnitude and types of interactions as they affect behavior, especially as it relates to operationally relevant performance (e.g., performance that depends on reaction time, procedural memory, etc.). In order to appropriately characterize this risk of multiple spaceflight environmental stressors, there is a recognition of the need to leverage research approaches using appropriate animal models and behavioral constructs. Very little has been documented on the combined effects of altered gravity, space radiation, and other psychological and cognitive stressors on the CNS. Preliminary evidence from rodents suggest that a combination of a minimum of exposures to even two of three stressors of: simulated space radiation, simulated microgravity, and simulated isolation and confinement, have produced different and more pronounced biological and performance effects than exposure to these same stressors individually. Structural and functional changes to the CNS of rodents exposed to transdisciplinary combined stressors indicate that important processes related to information processing are likely altered including impairment of exploratory and risk taking behaviors, as well as executive function including learning, memory, and cognitive flexibility — all of which may be linked to changes in related operational relevant performance. The fully integrated research plan outlines approaches to evaluate how combined, potentially synergistic, impacts of simultaneous exposures to spaceflight hazards will affect an astronaut’s CNS and their operationally relevant performance during future exploration missions, including missions to the Moon and Mars. The ultimate goals are to derive risk estimates for the combined, potentially synergistic, effects of the three major spaceflight hazards that will establish acceptable maximum decrement or change in a physiological or behavioral parameters during or after spaceflight, the acceptable limit of exposure to a spaceflight factor, and to evaluate strategies to mitigate any associated decrements in operationally relevant performance.

Steinberg, Susan L.↗
NASA NTRS2009

Digital Beamforming Scatterometer

This paper discusses scatterometer measurements collected with multi-mode Digital Beamforming Synthetic Aperture Radar (DBSAR) during the SMAP-VEX 2008 campaign. The 2008 SMAP Validation Experiment was conducted to address a number of specific questions related to the soil moisture retrieval algorithms. SMAP-VEX 2008 consisted on a series of aircraft-based.flights conducted on the Eastern Shore of Maryland and Delaware in the fall of 2008. Several other instruments participated in the campaign including the Passive Active L-Band System (PALS), the Marshall Airborne Polarimetric Imaging Radiometer (MAPIR), and the Global Positioning System Reflectometer (GPSR). This campaign was the first SMAP Validation Experiment. DBSAR is a multimode radar system developed at NASA/Goddard Space Flight Center that combines state-of-the-art radar technologies, on-board processing, and advances in signal processing techniques in order to enable new remote sensing capabilities applicable to Earth science and planetary applications [l]. The instrument can be configured to operate in scatterometer, Synthetic Aperture Radar (SAR), or altimeter mode. The system builds upon the L-band Imaging Scatterometer (LIS) developed as part of the RadSTAR program. The radar is a phased array system designed to fly on the NASA P3 aircraft. The instrument consists of a programmable waveform generator, eight transmit/receive (T/R) channels, a microstrip antenna, and a reconfigurable data acquisition and processor system. Each transmit channel incorporates a digital attenuator, and digital phase shifter that enables amplitude and phase modulation on transmit. The attenuators, phase shifters, and calibration switches are digitally controlled by the radar control card (RCC) on a pulse by pulse basis. The antenna is a corporate fed microstrip patch-array centered at 1.26 GHz with a 20 MHz bandwidth. Although only one feed is used with the present configuration, a provision was made for separate corporate feeds for vertical and horizontal polarization. System upgrades to dual polarization are currently under way. The DBSAR processor is a reconfigurable data acquisition and processor system capable of real-time, high-speed data processing. DBSAR uses an FPGA-based architecture to implement digitally down-conversion, in-phase and quadrature (I/Q) demodulation, and subsequent radar specific algorithms. The core of the processor board consists of an analog-to-digital (AID) section, three Altera Stratix field programmable gate arrays (FPGAs), an ARM microcontroller, several memory devices, and an Ethernet interface. The processor also interfaces with a navigation board consisting of a GPS and a MEMS gyro. The processor has been configured to operate in scatterometer, Synthetic Aperture Radar (SAR), and altimeter modes. All the modes are based on digital beamforming which is a digital process that generates the far-field beam patterns at various scan angles from voltages sampled in the antenna array. This technique allows steering the received beam and controlling its beam-width and side-lobe. Several beamforming techniques can be implemented each characterized by unique strengths and weaknesses, and each applicable to different measurement scenarios. In Scatterometer mode, the radar is capable to.generate a wide beam or scan a narrow beam on transmit, and to steer the received beam on processing while controlling its beamwidth and side-lobe level. Table I lists some important radar characteristics

Rincon, Rafael F.↗
NASA NTRS1994

Parallel grid generation algorithm for distributed memory computers

A parallel grid-generation algorithm and its implementation on the Intel iPSC/860 computer are described. The grid-generation scheme is based on an algebraic formulation of homotopic relations. Methods for utilizing the inherent parallelism of the grid-generation scheme are described, and implementation of multiple levELs of parallelism on multiple instruction multiple data machines are indicated. The algorithm is capable of providing near orthogonality and spacing control at solid boundaries while requiring minimal interprocessor communications. Results obtained on the Intel hypercube for a blended wing-body configuration are used to demonstrate the effectiveness of the algorithm. Fortran implementations bAsed on the native programming model of the iPSC/860 computer and the Express system of software tools are reported. Computational gains in execution time speed-up ratios are given.

Moitra, Stuti↗
DOE OSTI2021

The ATLAS Fast TracKer system

The ATLAS Fast TracKer (FTK) was designed to provide full tracking for the ATLAS high-level trigger by using pattern recognition based on Associative Memory (AM) chips and fitting in high-speed field programmable gate arrays. The tracks found by the FTK are based on inputs from all modules of the pixel and silicon microstrip trackers. The as-built FTK system and components are described, as is the online software used to control them while running in the ATLAS data acquisition system. Also described is the simulation of the FTK hardware and the optimization of the AM pattern banks. An optimization for long-lived particles with large impact parameter values is included. A test of the FTK system with the data playback facility that allowed the FTK to be commissioned during the shutdown between Run 2 and Run 3 of the LHC is reported. The resulting tracks from part of the FTK system covering a limited $\eta$-$\phi$ region of the detector are compared with the output from the FTK simulation. It is shown that FTK performance is in good agreement with the simulation.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2026

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗
NASA NTRS1994

High Performance FORTRAN

High performance FORTRAN is a set of extensions for FORTRAN 90 designed to allow specification of data parallel algorithms. The programmer annotates the program with distribution directives to specify the desired layout of data. The underlying programming model provides a global name space and a single thread of control. Explicitly parallel constructs allow the expression of fairly controlled forms of parallelism in particular data parallelism. Thus the code is specified in a high level portable manner with no explicit tasking or communication statements. The goal is to allow architecture specific compilers to generate efficient code for a wide variety of architectures including SIMD, MIMD shared and distributed memory machines.

Mehrotra, Piyush↗