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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,099 records · Page 61
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Zika virus detection using antibody-immobilized disposable cover glass and AlGaN/GaN high electron mobility transistors

Zika virus detection was demonstrated using antibody-functionalized cover glasses externally connected to the gate electrode of an AlGaN/GaN high electron mobility transistor (HEMT). A pulsed bias voltage of 0.5 V was applied to an electrode on the region of the cover glass region functionalized with antibody, and the resulting changes of drain current of the HEMT were employed to determine the presence of Zika virus antigen concentration ranging from 0.1 to 100 ng/ml. The dynamic and static drain current changes as a function of Zika virus concentration were modeled with a spring-like elastic relaxation model and the Langmuir extension model, respectively. Excellent fits to the data were found with relaxation time constants of antibody and antigen molecules in the range of 11 μs and 0.66–24.4 μs, respectively, for the concentration range investigated. The ratio of antibody bound with antigen to the total available antibody on the functionalized contact window was in the range of 0.013–0.84 for the Zika antigen concentration range of 0.1–100 ng/ml. Since the HEMT is not exposed to the bio-solution, it can be used repeatedly. Here, the functionalized glass is the only disposable part in the detection system, showing the potential of this approach for hand-held, low cost sensor packages for point-of-care applications.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2018

A single electron transistor charge sensor in strong rf fields

We measure the charge sensitivity, S e , of a single electron transistor (SET) in the presence of strong (V rf ~ e/C g ) spurious radio frequency (rf) signals at frequencies up to 50 MHz, where C g is the gate capacitance. Although S e appears to degrade when exposed to V rf , we find that broadening of conduction peaks is largely due to the measurement technique and show that S e is maintained even with strong V rf present. We show cancellation of a known V rf signal at 1 MHz, demonstrating that a stable bias point in the presence of rf signals is possible.

47 OTHER INSTRUMENTATION↗
DOE OSTI2018

Effects of nitrogen on the interface density of states distribution in 4H-SiC metal oxide semiconductor field effect transistors: Super-hyperfine interactions and near interface silicon vacancy energy levels

The performance of silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is greatly enhanced by a post-oxidation anneal in NO. These anneals greatly improve effective channel mobilities and substantially decrease interface trap densities. In this work, we investigate the effect of NO anneals on the interface density of states through density functional theory (DFT) calculations and electrically detected magnetic resonance (EDMR) measurements. EDMR measurements on 4H-silicon carbide (4H-SiC) MOSFETs indicate that NO annealing substantially reduces the density of near interface SiC silicon vacancy centers: it results in a 30-fold reduction in the EDMR amplitude. The anneal also alters post-NO anneal resonance line shapes significantly. EDMR measurements exclusively sensitive to interface traps with near midgap energy levels have line shapes relatively unaffected by NO anneals, whereas the measurements sensitive to defects with energy levels more broadly distributed in the 4H-SiC bandgap are significantly altered by the anneals. Using DFT, we show that the observed change in EDMR linewidth and the correlation with energy levels can be explained by nitrogen atoms introduced by the NO annealing substituting into nearby carbon sites of silicon vacancy defects.

42 ENGINEERING↗
DOE OSTI2019

Integrated high electron mobility transistors in GaAs/AlGaAs heterostructures for amplification at sub-Kelvin temperatures

Here, we demonstrate the use of custom high electron mobility transistors (HEMTs) fabricated in GaAs/AlGaAs heterostructures to amplify current from quantum dot devices. The amplifier circuit is located adjacent to the quantum dot device, at sub-Kelvin temperatures, in order to reduce the impact of cable capacitance and environmental noise. Using this circuit, we show a current gain of 380 for 0.56 μW of power dissipation, with a bandwidth of 2.7 MHz and current noise referred to the input of 24 fA/Hz 1/2 for frequencies of 0.1–1 MHz. The power consumption required for similar gain is reduced by more than a factor of 20 compared to a previous demonstration using a commercial off-the-shelf HEMT. Lastly, we also demonstrate integration of a HEMT amplifier circuit on-chip with a quantum dot device, which has the potential to reduce parasitics and should allow for more complex circuits with reduced footprints.

42 ENGINEERING↗
DOE OSTI2019

Delta-doped SrTiO 3 top-gated field effect transistor

Oxide heterostructures are an enticing platform for incorporation in field-effect transistors (FETs) due to their diverse physical properties which can be tuned by electrostatic gating. Here, we discuss a top-gated FET based on a SrTiO 3 delta-doped structure, which operates down to cryogenic temperatures. The device shows excellent DC characteristics with an on/off ratio greater than 10 4 and field effect mobility estimated to be 2125 cm 2 /V s at 2 K. The high field effect mobility was consistent with the Hall mobility and is attributed to the formation of a two-dimensional electron system in the delta-doped layer: two-dimensional gate-tunable Shubnikov-de Haas oscillations confirm this. The achievement of an electron density of 3 × 10 12 cm –2 in a gate-tunable geometry allows for the exploration of the interplay between magnetic, ferroelectric, and superconducting properties of SrTiO 3 in the quantum limit.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2019

Multidimensional thermal analysis of an ultrawide bandgap AlGaN channel high electron mobility transistor

Improvements in radio frequency and power electronics can potentially be realized with ultrawide bandgap materials such as aluminum gallium nitride (AlxGa 1-x N). Multidimensional thermal characterization of an Al 0.30 Ga 0.70 N channel high electron mobility transistor (HEMT) was done using Raman spectroscopy and thermoreflectance thermal imaging to experimentally determine the lateral and vertical steady-state operating temperature profiles. An electrothermal model of the Al 0.30 Ga 0.70 N channel HEMT was developed to validate the experimental results and investigate potential device-level thermal management. While the low thermal conductivity of this III-N ternary alloy system results in more device self-heating at room temperature, the temperature insensitive thermal and electrical output characteristics of Al x Ga 1-x N may open the door for extreme temperature applications.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Experimental and modeling study of 1/ f noise in multilayer MoS2 and MoSe2 field-effect transistors

In field-effect transistors (FETs) with two-dimensional (2D) transition metal dichalcogenide channels, the dependence of field-effect mobility on atomic layer thickness has been studied and interpreted in terms of interface scattering and interlayer coupling resistance (Rint). However, a model for 1/f noise, such as in MoS2 and in MoSe2 FETs, for various contact metals and layer number thicknesses has not been reported. In this work, we have experimentally studied current–voltage and 1/f noise on MoS2 and MoSe2 FETs with source and drain contacts of high and low work function metals to understand both the mobility and the noise behavior. We have developed a noise model incorporating layer number dependent Hooge parameters and Rint. The noise and mobility models utilize screening lengths for charge, mobility, and Hooge parameter to describe the variation of these quantities with a layer number. Using our single model topology with appropriate fitting parameters for each material and each contact metal, the model captures the experimentally observed layer thickness dependence of the Hooge parameter. Our noise analysis is fully comprehensive and, hence, could be applied to any 2D layered systems.

Kwon, Jiseok↗
DOE OSTI2021

Effects of polymer grain boundary passivation on organic–inorganic hybrid perovskite field-effect transistors

Despite successful applications of solution-processed organic–inorganic hybrid perovskites (OIHPs) such as archetypical methylammonium lead iodide (MAPI) in high-performance optoelectronic devices including solar cells and light emitting diodes, their application in field-effect transistors (FETs) remains relatively limited due to the unresolved issues caused by ion migration in OIHPs, such as screening of gate electric fields, lowered device on-off ratios and field-effect mobility, and large hysteresis in the FET transfer characteristics. Here, we report improved performances of the MAPI-based FET via a polymer-additive-based grain boundary (GB) passivation approach that suppresses the ion migration. Polycaprolactone (PCL) was incorporated into the MAPI FET as a GB-passivation additive as confirmed by scanning electron and atomic force microscopies. Unlike the typical n-type behavior and large transfer hysteresis in the starting, pristine MAPI FETs, the GB passivation by PCL led to a drastically reduced hysteresis in FET transfer characteristics, while hinting at an ambipolar transport and slight improvement in mobility, indicating a reduced ion migration in the PCL-incorporated MAPI FET. The effect of PCL GB passivation in suppressing ion migration was directly confirmed by the measured, increased activation energy for ion migration in the PCL-incorporated MAPI. Here, the results not only represent the first report of the polymer-additive-based mitigation of the ion migration in the MAPI FET but also suggest potential utilities of the approach for enabling high-performance OIHP FETs and electronic devices in general.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2024

Low temperature recovery of OFF-state stress induced degradation of AlGaN/GaN high electron mobility transistors

Thermal annealing is a widely used strategy to enhance semiconductor device performance. However, the process is complex for multi-material multi-layered semiconductor devices, where thermoelastic stresses from lattice constant and thermal expansion coefficient mismatch may create more defects than those annealed. We propose an alternate low temperature annealing technique, which utilizes the electron wind force (EWF) induced by small duty cycle high density pulsed current. To demonstrate its effectiveness, we intentionally degrade AlGaN/GaN high electron mobility transistors (HEMTs) with accelerated OFF-state stressing to increase ON-resistance ∼182.08% and reduce drain saturation current ∼85.82% of pristine condition at a gate voltage of 0 V. We then performed the EWF annealing to recover the corresponding values back to ∼122.21% and ∼93.10%, respectively. The peak transconductance, degraded to ∼76.58% of pristine at the drain voltage of 3 V, was also recovered back to ∼92.38%. This recovery of previously degraded transport properties is attributed to approximately 80% recovery of carrier mobility, which occurs during EWF annealing. We performed synchrotron differential aperture x-ray microscopy measurements to correlate these annealing effects with the lattice structural changes. We found a reduction of lattice plane spacing of (001) planes and stress within the GaN layer under the gate region after EWF annealing, suggesting a corresponding decrease in defect density. Application of this low-temperature annealing technique for in-operando recovery of degraded electronic devices is discussed.

Physics↗
DOE OSTI2021

High performance ionic-liquid-gated air doped diamond field-effect transistors

Here we report successful fabrication of high performance ion-gated field-effect transistors (FETs) on hydrogenated diamond surface. Investigations on the hydrogen (H)-terminated diamond by Hall effect measurements shows Hall mobility as high as ~200 cm 2 V –1 s –1 . In addition we demonstrate a rapid fabrication scheme for achieving stable high performance devices useful for determining optimal growth and fabrication conditions. We achieved H-termination using hydrogen plasma treatment with a sheet resistivity as low as ~1.3 kΩ/sq. Conductivity through the FET channel is studied as a function of bias voltage on the liquid ion-gated electrode from –3.0 to 1.5 V. Stability of the H-terminated diamond surface was studied by varying the substrate temperature up to 350 °C. It was demonstrated that the sheet resistance and carrier densities remain stable over 3 weeks in ambient air atmosphere even at substrate temperatures up to 350 °C, whereas increasing temperature beyond this limit has effected hydrogenation. This study opens new avenues for carrying out fundamental research on diamond FET devices with ease of fabrication and high throughput.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2021

First demonstration of robust tri-gate β-Ga 2 O 3 nano-membrane field-effect transistors

Nano-membrane tri-gate β-gallium oxide (β-Ga 2 O 3 ) field-effect transistors (FETs) on SiO 2 /Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between β-Ga 2 O 3 and gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (Al 2 O 3 ) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV dec –1 , high drain current (I DS ) ON/OFF ratio of 1.5 × 10 9 , and negligible transfer characteristic hysteresis. Furthermore, we also experimentally demonstrated robustness of these devices with current–voltage (I–V) characteristics measured at temperatures up to 400 °C.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2019

High-throughput fabrication and semi-automated characterization of oxide thin film transistors

High throughput experimental methods are known to accelerate the rate of research, development, and deployment of electronic materials. For example, thin films with lateral gradients in composition, thickness, or other parameters have been used alongside spatiallyresolved characterization to assess how various physical factors affect material properties under varying measurement conditions. Similarly, multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance. In this work, we apply these high throughput experimental methods to thin film transistors (TFTs), demonstrating combinatorial device fabrication and semiautomated characterization using sputtered oxide TFTs as a case study. Here, we show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library, such as channel thickness and length, channel cation compositions, and oxygen atmosphere during deposition. We also present a semi-automated method to measure the 44 devices fabricated on a 50x50mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time. Finally, we propose a fully automated characterization system for similar TFT libraries, which can be coupled with high throughput data analysis. These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Radiation Tolerance of 65nm CMOS Transistors

We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Space-Charge-Limited van der Waals Spin Transistor

Integrating semiconducting and magnetic materials could combine transistorlike operation with nonvolatility and enable architectures such as logic in memory. Here, in this work, we employ correlated electrical transport and scanning nitrogen-vacancy center magnetic imaging to elucidate a spin transistor concept that amalgamates vertical and lateral hopping transport inside a 2D antiferromagnetic semiconductor, mechanistically distinct from vertical tunneling devices. Our device, based on a monolayer-bilayer junction in CrSBr, displays giant, gate-tunable magnetoresistance driven by the dual action of electrostatic doping on space-charge-limited lateral conduction and interlayer exchange coupling. Moreover, we visualize a field-trainable, layer-sharing effect that selects between coherent or domain-wall reversal at the spin-flip transition, enabling multilevel, memristive conductance states. Our layer-dependent space charge mechanism for convergent electrical and magnetic control opens opportunities to address limitations in contemporary computing.

2-dimensional systems↗
DOE OSTI2018

High precision gate signal timing control based active voltage balancing scheme for series-connected fast switching field-effect transistors

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

Zhang, Zheyu↗
DOE OSTI2021

Switching Characteristics of a 1.2 kV, 50 mΩ SiC Monolithic Bidirectional Field Effect Transistor (BiDFET) with Integrated JBS Diodes

—The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.

Silicon Carbide, Monolithic, Bidirectional, FourQu↗
DOE OSTI2020

Demonstrating the GaInP/GaAs Three-Terminal Heterojunction Bipolar Transistor Solar Cell

The three-terminal heterojunction bipolar transistor solar cell (HBTSC) concept enables the realization of a monolithic double-junction device with individual current extraction. We present an HBTSC realized by a heterojunction of GaInP and GaAs. The one-sun open-circuit voltage (V OC ) of the top and bottom junctions are 1.33 V and 0.99 V, respectively, while fill factors (FF) are above 80%. At one-sun illumination, reducing one junction's bias from V OC to maximum power point degrades the performance of the other junction only slightly (<; 0.5% efficiency loss). These results demonstrate the potential of the HBTSC concept to produce high-efficiency independently connected double-junction solar cells.

14 SOLAR ENERGY↗
DOE OSTI2021

Inverted GaInP/GaAs Three-Terminal Heterojunction Bipolar Transistor Solar Cell

Here we present the experimental results of an inverted three-terminal heterojunction bipolar transistor solar cell (HBTSC) made of GaInP/GaAs. The inverted growth and processing enables contacting the intermediate layer from the bottom, which increases the cell performance by reducing shadow factor and series resistance at the same time. With this prototype we show that an inverted processing of a three-terminal solar cell is feasible and pave the way for the application of epitaxial lift-off, substrate reuse and mechanical stacking to the HBTSC which can eventually lead to a low-cost high-efficiency III-V-on-Si HBTSC technology.

41 EE - Solar Energy Technologies Office (EE-4S)↗