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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,099 records · Page 61
All sourcesNASA NTRSDOE OSTI
NASA NTRS2019

High-Performance Spaceflight Computing (HPSC) Middleware Overview

High Performance Spacecraft Computing (HPSC) is a joint project between the National Aeronautics and Space Administration (NASA) and Air Force Research Lab (AFRL) to develop a high-performance multi-core radiation hardened flight processor. HPSC offers a new flight computing architecture to meet the needs of NASA missions through 2030 and beyond. Providing on the order of 100X the computational capacity of current flight processors for the same amount of power, the multicore architecture of the HPSC processor, or "Chiplet" provides unprecedented flexibility in a flight computing system by enabling the operating point to be set dynamically, trading among needs for computational performance, energy management and fault tolerance. The HPSC Chiplet is being developed by Boeing under contract to NASA, and is expected to provide prototypes in 2021. The HPSC Chiplet prototypes will be delivered with an evaluation board, system emulators, comprehensive system software, and a software development kit. In addition to the vendor deliverables, the AFRL is funding the development of a flexible Middleware to be developed by NASA Jet Propulsion Laboratory and NASA Goddard Space Flight Center. The HPSC Middleware provides a suite of thirteen high level services to manage the compute, memory and I/O resources of this complex device.This presentation will provide an overview of the HPSC project, including a hardware overview, system software overview, Middleware overview, and mission use cases. The hardware overview will provide a look at the 8 core High Performance Processing Subsystem (HPPS), the Real Time Processing Subsystem (RTPS), the Chiplet Configuration Management Subsystem, on chip peripherals, and high speed I/O. The system software overview will introduce the boot loaders, operating systems, device drivers, and software development environment. The Middleware overview will provide insight into the high-level services that will be provided to help mission developers manage the many resources and configurations made possible with the Chiplet. Finally, the presentation will provide a brief look at the mission use cases that can be enabled with this next generation architecture.

middleware↗
DOE OSTI2020

Monitor support on accelerated processing device

A technique for implementing synchronization monitors on an accelerated processing device (“APD”) is provided. Work on an APD includes workgroups that include one or more wavefronts. All wavefronts of a workgroup execute on a single compute unit. A monitor is a synchronization construct that allows workgroups to stall until a particular condition is met. Responsive to all wavefronts of a workgroup executing a wait instruction, the monitor coordinator records the workgroup in an “entry queue.” The workgroup begins saving its state to a general APD memory and, when such saving is complete, the monitor coordinator moves the workgroup to a “condition queue.” When the condition specified by the wait instruction is met, the monitor coordinator moves the workgroup to a “ready queue,” and, when sufficient resources are available on a compute unit, the APD schedules the ready workgroup for execution on a compute unit.

42 ENGINEERING↗
DOE OSTI2020

Data-Driven Day-Ahead PV Estimation Using Autoencoder-LSTM and Persistence Model

Inherent variability in photovoltaic (PV) and associated impacts on power systems is a challenging problem for both the PV owners and the grid operators. Existing statistical and machine learning algorithms typically work well for weather conditions similar to historical data. Furthermore, uncertain weather conditions pose a great challenge to the estimation accuracy of the estimation models. With the enhanced integration of intelligent electronic devices and the realization of associated automation in the power grid, renewable energy data is becoming more accessible, which can be utilized by deep learning models and improve the PV power generation estimation accuracy. In this paper, a hybrid deep learning model driven by external weather data is proposed to do day-ahead PV output forecasting at 15-minute-interval. The proposed model is motivated by the recent advancement of Long-Short-Term-Memory (LSTM) networks and AutoEncoder (AE), which estimates uncertainties in sequence while making the prediction for complex weather conditions. Meanwhile, the persistence model (PM) is used to predict continuous sunny weather conditions. The forecasting result is validated with data from multiple locations

42 ENGINEERING↗
DOE OSTI2020

Redox transistors based on TiO 2 for analogue neuromorphic computing

The ability to train deep neural networks on large data sets have made significant impacts onto artificial intelligence, but consume significant amounts of energy due to the need to move information from memory to logic units. In-memory "neuromorphic" computing presents an alternative framework that processes information directly on memory elements. In-memory computing has been limited by the poor performance of the analogue information storage element, often phase-change memory or memristors. To solve this problem, we developed two types of "redox transistors" using TiO 2 (anatase) which stores analogue information states through the electrochemical concentration of dopants in the crystal. The first type of redox transistor uses lithium as the electrochemical dopant ion, and its key advantage is low operating voltage. The second uses oxygen vacancies as the dopant, which is CMOS compatible and can retain state even when scaled to nanosized dimensions. Both devices offer significant advantages in terms of predictable analogue switching over conventional filamentary-based devices, and provide a significant advance in developing materials and devices for neuromorphic computing.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Record thermopower found in an IrMn-based spintronic stack

The Seebeck effect converts thermal gradients into electricity. As an approach to power technologies in the current Internet-of-Things era, on-chip energy harvesting is highly attractive, and to be effective, demands thin film materials with large Seebeck coefficients. In spintronics, the antiferromagnetic metal IrMn has been used as the pinning layer in magnetic tunnel junctions that form building blocks for magnetic random access memories and magnetic sensors. Spin pumping experiments revealed that IrMn Néel temperature is thickness-dependent and approaches room temperature when the layer is thin. Here, we report that the Seebeck coefficient is maximum at the Néel temperature of IrMn of 0.6 to 4.0 nm in thickness in IrMn-based half magnetic tunnel junctions. We obtain a record Seebeck coefficient 390 (±10) μV K -1 at room temperature. Our results demonstrate that IrMn-based magnetic devices could harvest the heat dissipation for magnetic sensors, thus contributing to the Power-of-Things paradigm.

42 ENGINEERING↗
DOE OSTI2022

Er-doped anatase TiO 2 thin films on LaAlO 3 (001) for quantum interconnects (QuICs)

Rare-earth ions (REIs) doped into solid-state crystal hosts offer an attractive platform for realizing quantum interconnects that can function as quantum memories and quantum repeaters. The 4f valence electrons of REIs are shielded by 5s and 5p electrons and undergo highly coherent transitions even when embedded in host crystals. In particular, Er 3+ has an optical transition in the telecom band that is suitable for low-loss communication. Recently, REIs in thin film systems have gained interest due to potential advantages in providing a flexible host crystal environment, enabling scalable on-chip integration with other quantum devices. Here, we investigate the structural and optical properties of Er-doped anatase TiO 2 thin films on LaAlO 3 (001) substrates. By choosing a system with minimal lattice mismatch and adjusting Er-dopant concentration, we achieve optical inhomogeneous linewidths of 5 GHz at 4.5 K. Furthermore, we show that 9 nm-thick buffer and capping layers can reduce the linewidth by more than 40%, suggesting a pathway to further narrowing linewidths in this system. We also identify that Er 3+ ions mainly incorporate into substitutional Ti 4+ sites with non-polar D 2d symmetry, which makes Er dopants insensitive to the first order to local electric fields from impurities and is desirable for coherence properties of Er 3+ spins.

42 ENGINEERING↗
NASA NTRS1995

Monitoring Composite Material Pressure Vessels with a Fiber-Optic/Microelectronic Sensor System

We discuss the concept of an integrated, fiber-optic/microelectronic distributed sensor system that can monitor composite material pressure vessels for Air Force space systems to provide assessments of the overall health and integrity of the vessel throughout its entire operating history from birth to end of life. The fiber optic component would include either a semiconductor light emitting diode or diode laser and a multiplexed fiber optic sensing network incorporating Bragg grating sensors capable of detecting internal temperature and strain. The microelectronic components include a power source, a pulsed laser driver, time domain data acquisition hardware, a microprocessor, a data storage device, and a communication interface. The sensing system would be incorporated within the composite during its manufacture. The microelectronic data acquisition and logging system would record the environmental conditions to which the vessel has been subjected to during its storage and transit, e.g., the history of thermal excursions, pressure loading data, the occurrence of mechanical impacts, the presence of changing internal strain due to aging, delamination, material decomposition, etc. Data would be maintained din non-volatile memory for subsequent readout through a microcomputer interface.

Klimcak, C.↗
DOE OSTI2020

High performance context switching for virtualized FPGA accelerators

A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

42 ENGINEERING↗
DOE OSTI2022

Automatic Differentiation of C++ Codes on Emerging Manycore Architectures with Sacado

Automatic differentiation (AD) is a well-known technique for evaluating analytic derivatives of calculations implemented on a computer, with numerous software tools available for incorporating AD technology into complex applications. However, a growing challenge for AD is the efficient differentiation of parallel computations implemented on emerging manycore computing architectures such as multicore CPUs, GPUs, and accelerators as these devices become more pervasive. In this work, we explore forward mode, operator overloading-based differentiation of C++ codes on these architectures using the widely available Sacado AD software package. In particular, we leverage Kokkos, a C++ tool providing APIs for implementing parallel computations that is portable to a wide variety of emerging architectures. Here we describe the challenges that arise when differentiating code for these architectures using Kokkos, and two approaches for overcoming them that ensure optimal memory access patterns as well as expose additional dimensions of fine-grained parallelism in the derivative calculation. We describe the results of several computational experiments that demonstrate the performance of the approach on a few contemporary CPU and GPU architectures. We then conclude with applications of these techniques to the simulation of discretized systems of partial differential equations.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1988

Development of a high-speed H-alpha camera system for the observation of rapid fluctuations in solar flares

A solid-state digital camera was developed for obtaining H alpha images of solar flares with 0.1 s time resolution. Beginning in the summer of 1988, this system will be operated in conjunction with SMM's hard X-ray burst spectrometer (HXRBS). Important electron time-of-flight effects that are crucial for determining the flare energy release processes should be detectable with these combined H alpha and hard X-ray observations. Charge-injection device (CID) cameras provide 128 x 128 pixel images simultaneously in the H alpha blue wing, line center, and red wing, or other wavelength of interest. The data recording system employs a microprocessor-controlled, electronic interface between each camera and a digital processor board that encodes the data into a serial bitstream for continuous recording by a standard video cassette recorder. Only a small fraction of the data will be permanently archived through utilization of a direct memory access interface onto a VAX-750 computer. In addition to correlations with hard X-ray data, observations from the high speed H alpha camera will also be correlated and optical and microwave data and data from future MAX 1991 campaigns. Whether the recorded optical flashes are simultaneous with X-ray peaks to within 0.1 s, are delayed by tenths of seconds or are even undetectable, the results will have implications on the validity of both thermal and nonthermal models of hard X-ray production.

Kiplinger, Alan L.↗
NASA NTRS1989

Effects of space radiation on electronic microcircuits

The single event effects or phenomena (SEP), which so far have been observed as events falling on one or another of the SE classes: Single Event Upset (SEU), Single Event Latchup (SEL) and Single Event Burnout (SEB), are examined. Single event upset is defined as a lasting, reversible change in the state of a multistable (usually bistable) electronic circuit such as a flip-flop or latch. In a computer memory, SEUs manifest themselves as unexplained bit flips. Since latchup is in general caused by a single event of short duration, the single event part of the SEL term is superfluous. Nevertheless, it is used customarily to differentiate latchup due to a single heavy charged particle striking a sensitive cell from more ordinary kinds of latchup. Single event burnout (SEB) refers usually to total instantaneous failure of a power FET when struck by a single particle, with the device shorting out the power supply. An unforeseen failure of these kinds can be catastrophic to a space mission, and the possibilities are discussed.

Kolasinski, W. A.↗
NASA NTRS2008

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Phillips, Thomas A.↗
NASA NTRSDate not supplied

Delay Tolerant, Radio Frequency Identification (RFID )-enabled Sensing

Radio Frequency Identification (RFID) technology offers a completely passive method to transmit fixed data sequences from an RFID tag, which typically doesn’t have its own power supply, to an interrogator. Radio frequency (RF) energy harvested from the interrogator is rectified by the tag and used to charge an integrated circuit (IC). The IC then modulates the received signal with the data stored on the tag and reflects the energy back to the interrogator. RFID has seen great proliferation in terrestrial inventory management applications, and it has recently made the jump to spaceflight applications onboard the International Space Station, augmenting an existing optical bar‐code infrastructure for tracking supplies. A number of advanced automated logistics management (ALM) concepts employing RFID are currently being developed and evaluated, including so‐called “smart” shelves, cubbies, and trash receptacles using low‐power, embeddable RFID interrogators. An infrastructure where both crew members and robotic assistants, such as autonomous free flyers, are similarly equipped with small RFID interrogators seems likely. It therefore behooves us to consider extending this infrastructure beyond ALM to applications such as low power, embedded sensing. Typically, data on an RFID tag can only be written by an RFID interrogator, using interrogator energy. In recent years, however, a few efforts have focused on using that energy to drive data acquisition from the tag IC, allowing the tag to modify its stored data sequence with sensor data before replying to an interrogator. In this way, the tag can act as a completely passive sensing device. One problem exists with this approach, however: the tag cannot gather data when an interrogator is not present. Thus, strictly passive RFID sensing tags cannot gather data at regular intervals, in the manner of a typical wireless sensor network, without careful, and impractical, planning of mobile interrogator movements. To address this shortcoming, we look to a recent advance in RFID technology which allows an external microprocessor to power the tag IC and write directly into its RFID memory using a wired serial interface. In this paradigm, data gathering is driven by a small, on‐board power supply (using batteries or harvested energy), and data transfer is provided passively through the RFID interrogation service. Since communication typically consumes the lion’s share of power in WSNs, such a technique has the potential to enable extremely long‐lived, embedded wireless sensing when used with extremely low‐current microcontrollers. Since the communication channel is only open when an interrogator is present and actively interrogating the RFID sensing tag, transport of periodically‐sampled sensor data presents itself as a delay/disruption‐tolerant networking (DTN) problem. In this paper, we present the design of a DTN‐like overlay on the common EPC Global, Class 1, Generation 2 RFID standard. This overlay allows seamless, guaranteed data transfer using the EPC Global protocol, supporting extremely low‐power, embedded sensing using an infrastructure likely to be already in place for ALM applications. We evaluate a prototype implementation of a complete end‐to‐end system using a robotic RFID interrogation agent, and we present future directions for the development of this sensing technique.

Raymond S. Wagner↗
NASA NTRS1978

Implementation of real-time digital signal processing systems

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Narasimha, M.↗
NASA NTRS1999

Fabrication system, method and apparatus for microelectromechanical devices

A fabrication system and method of fabrication for producing microelectromechanical devices such as field-effect displays using thin-film technology. A spacer is carried at its proximal end on the surface of a substrate having field-effect emitters with the spacer being enabled for tilting movement from a nested position to a deployed position which is orthogonal to the plane of the substrate. An actuator is formed with one end connected with the substrate and another end connected with spacer. The actuator is made of a shape memory alloy material which contracts when heated through the material's phase-change transition temperature. Contraction of the actuator exerts a pulling force on the spacer which is tilted to the deployed position. A plurality of the spacers are distributed over the area of the display. A glass plate having a phosphor-coated surface is fitted over the distal ends of the deployed spacer.

Johnson, A. David↗
DOE OSTI2025

Unified architecture for quantum lookup tables

Quantum access to arbitrary classical data encoded in unitary black-box oracles underlies interesting data-intensive quantum algorithms, such as machine learning or electronic structure simulation. The feasibility of these applications depends crucially on gate-efficient implementations of these oracles, which are commonly some reversible versions of the Boolean circuit for a classical lookup table. Here, we present a general parametrized architecture for quantum circuits implementing a lookup table that encompasses all prior work in realizing a continuum of optimal trade-offs between qubits, non-Clifford gates, and error resilience, up to logarithmic factors. Our architecture assumes only local 2D connectivity, yet recovers results, with the appropriate parameters, polylogarithmic error scaling. We also identify regimes, such as simultaneous sublinear scaling, in all parameters. These results enable tailoring implementations of the commonly used lookup table primitive to any given quantum device with constrained resources.

quantum circuits↗
DOE OSTI2020

The Computational Capacity of Mem-LRC Reservoirs

Reservoir computing has a emerged as a powerful tool in data-driven time series analysis. The possibility of utilizing hardware reservoirs as specialized co-processors has generated interest in the properties of electronic reservoirs, especially those based on memristors as the nonlinearity of these devices should translate to an improved nonlinear computational capacity of the reservoir. However, designing these reservoirs requires a detailed understanding of how memristive networks process information which has thus far been lacking. In this work, we derive an equation for general memristor-inductor-resistor-capacitor (MEM-LRC) reservoirs that includes all network and dynamical constraints explicitly. Utilizing this we undertake a study of the computational capacity of these reservoirs. We demonstrate that hardware reservoirs may be constructed with extensive memory capacity and that the presence of memristors enacts a tradeoff between memory capacity and nonlinear computational capacity. Here, using these principles, we design reservoirs to tackle problems in signal processing, paving the way for applying hardware reservoirs to high-dimensional spatiotemporal systems.

Circuits with memory↗
NASA NTRS1973

Electro-optical processing of phased array data

An on-line spatial light modulator for application as the input transducer for a real-time optical data processing system is described. The use of such a device in the analysis and processing of radar data in real time is reported. An interface from the optical processor to a control digital computer was designed, constructed, and tested. The input transducer, optical system, and computer interface have been operated in real time with real time radar data with the input data returns recorded on the input crystal, processed by the optical system, and the output plane pattern digitized, thresholded, and outputted to a display and storage in the computer memory. The correlation of theoretical and experimental results is discussed.

Casasent, D.↗