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At least 1,099 records · Page 61

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗

Open Circuit Switch Fault Management Method of a Multi-Phase Synchronous Buck Converter for EV Charging Application

Multi-phase synchronous buck converter (MSBC) is becoming popular for the electric vehicle (EV) charging application because of its higher efficiency, smaller passive component sizes, bidirectional power flow, and output current ripple reduction through interleaving. This converter also provides higher reliability than the traditional single phase converter since its modular structure enables fault tolerant operation. Fault management in the converter requires the detection of switch fault, shut down of the faulty phase, and reconfiguration of the PWM signals for the healthy phases to avoid circulating current and high output current ripple. In addition, it is desirable that the fault management method can be implemented using the micro-controller unit (MCU) or digital signal processor (DSP), which are widely used to control power converters. This paper presents a fault management method for detecting switch faults and reconfiguring healthy phases using a DSP. The method is validated through simulations and experiments using a commercial off-the-shelf power stack.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

The future of time and frequency dissemination

I will try to extrapolate the changes in the dissemination of time and frequency information that have taken place during the last 25 years to predict the future developments both in the methods of disseminating time and frequency and in the kinds of customers we will be asked to serve. Two important developments are likely to play pivotal roles in driving the evolution of dissemination. The first is the commercial availability of very high quality clocks -- devices whose performance may eventually rival that of the current generation of primary frequency standards. The widespread use of these devices may blur the traditional distinction between client and server, and may replace it with a more symmetrical interchange of data among peers. The second is the increasing demand for digital time and frequency information driven by the increasing sophistication of everything from traffic lights to electric power meters. The needs of these individual users may not tax the state of the art of primary frequency standards in principle, but their large numbers and wide geographical distribution present a technological challenge that is difficult to meet at a reasonable price using existing methods. Some of these problems may be solved (or at least addressed) using developments in communications and consumer electronics such as the increasing use of fiber-optic telephone circuits and the increasing bandwidth and sophistication of the cable network used to transmit television pictures. To be useful, these advances in hardware must stimulate parallel advances in software algorithms and methods. These advances are more difficult to predict with great confidence, but the developments of the last few years will be examined to provide some indications of the future.

Levine, Judah↗

NASA Tech Briefs, April 2013

Topics covered include: Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology; Nanoscale Surface Plasmonics Sensor With Nanofluidic Control; Advanced Dispersed Fringe Sensing Algorithm for Coarse Phasing Segmented Mirror Telescopes; Neural Network Back-Propagation Algorithm for Sensing Hypergols; Bulk Moisture and Salinity Sensor; Change-Based Satellite Monitoring Using Broad Coverage and Targetable Sensing; Circularly Polarized Microwave Antenna Element with Very Low Off-Axis Cross-Polarization; Ultra-Low Heat-Leak, High-Temperature Superconducting Current Leads for Space Applications; Flash Cracking Reactor for Waste Plastic Processing; An Automated Safe-to-Mate (ASTM) Tester; Wireless Chalcogenide Nanoionic-Based Radio-Frequency Switch; Compute Element and Interface Box for the Hazard Detection System; DOT Transmit Module; Composite Aerogel Multifoil Protective Shielding; Li-Ion Electrolytes with Improved Safety and Tolerance to High-Voltage Systems; Polymer-Reinforced, Non-Brittle, Lightweight Cryogenic Insulation; Controlled, Site-Specific Functionalization of Carbon Nanotubes with Diazonium Salts; Regenerable Sorbent for CO2 Removal; Sprayable Aerogel Bead Compositions With High Shear Flow Resistance and High Thermal Insulation Value; Lexan Linear Shaped Charge Holder with Magnets and Backing Plate; Robotic Ankle for Omnidirectional Rock Anchors; Wind, Wave, and Tidal Energy Without Power Conditioning; An Active Heater Control Concept to Meet IXO Type Mirror Module Thermal-Structural Distortion Requirement; Waterless Clothes-Cleaning Machine; Integrated Electrical Wire Insulation Repair System; LVGEMS Time-of-Flight Mass Spectrometry on Satellites; Surface Inspection Tool for Optical Detection of Surface Defects; Per-Pixel, Dual-Counter Scheme for Optical Communications; Certification-Based Process Analysis; Surface Navigation Using Optimized Waypoints and Particle Swarm Optimization; Smart-Divert Powered Descent Guidance to Avoid the Backshell Landing Dispersion Ellipse; Estimating Foreign-Object-Debris Density from Photogrammetry Data; Adaptive Sampling of Spatiotemporal Phenomena with Optimization Criteria; Building a 2.5D Digital Elevation Model From 2D Imagery; Eyes on the Earth 3D; Target Trailing With Safe Navigation for Maritime Autonomous Surface Vehicles; Adams-Based Rover Terramechanics and Mobility Simulator - ARTEMIS; ISTP CDF Skeleton Editor; Uplink Summary Generator (ULSGEN) Version 1.0; Robotics On-Board Trainer (ROBoT); Software Engineering Tools for Scientific Models; Automatic Data Filter Customization Using a Genetic Algorithm; Tracker Toolkit; Towards Efficient Scientific Data Management Using Cloud Storage; On a Formal Tool for Reasoning About Flight Software Cost Analysis; A Nanostructured Composites Thermal Switch Controls Internal and External Short Circuit in Lithium Ion Batteries; Spacecraft Crew Cabin Condensation Control; and Functional Near-Infrared Spectroscopy Signals Measure Neuronal Activity in the Cortex.

Source record↗

Accelerating computing for the future electric grid (CRADA Final Report)

As a participant in the Cyclotron Road Lab-Embedded Entrepreneurship Program (LEEP), Vellex Computing, Inc. has successfully validated the "Vellex Computing Stack," a breakthrough Analog Neural Computer (ANC) specifically designed for high-performance edge optimization. This project achieved critical milestones in mixed-signal circuit stability and software-hardware co-design, directly addressing national priorities in semiconductor resiliency. The success of this work is deeply rooted in the support from the Cyclotron Road LEEP, which provided the essential "hard tech" runway—funding, mentorship, and access to Lawrence Berkeley National Laboratory’s world-class characterization facilities—allowing Vellex to overcome the "Valley of Death" often faced by deep-tech hardware startups. By leveraging LBNL’s advanced testing infrastructure, Vellex was able to rigorously benchmark the ANC architecture against state-of-the-art digital solutions, a feat that would have been resource-prohibitive independently. This collaboration has not only advanced American leadership in analog computing but has also matured Vellex’s technology to a stage ripe for private sector commercialization.

24 POWER TRANSMISSION AND DISTRIBUTION↗

A Study of Linear Approximation Techniques for SAR Azimuth Processing

The application of the step transform subarray processing techniques to synthetic aperture radar (SAR) was studied. The subarray technique permits the application of efficient digital transform computational techniques such as the fast Fourier transform to be applied while offering an effective tool for range migration compensation. Range migration compensation is applied at the subarray level, and with the subarray size based on worst case range migration conditions, a minimum control system is achieved. A baseline processor was designed for a four-look SAR system covering approximately 4096 by 4096 SAR sample field every 2.5 seconds. Implementation of the baseline system was projected using advanced low power technologies. A 20 swath is implemented with approximately 1000 circuits having a power dissipation of from 70 to 195 watts. The baseline batch step transform processor is compared to a continuous strip processor, and variations of the baseline are developed for a wide range of SAR parameters.

Martinson, L. W.↗

Phase-Measuring System

System developed and used at Langley Research Center measures phase between two signals of same frequency or between two signals, one of which is harmonic multiple of other. Simple and inexpensive device combines digital and analog components to give accurate phase measurements. One signal at frequency f fed to pulse shaper, produces negative pulse at time t4. Pulse applied to control input of sample-and-hold module 1. Second signal, at frequency nf, fed to zero-crossover amplifier, producing square wave at time t. Signal drives first one-shot producing narrow negative pulse at t1. Signal then drives second one-shot producing narrow positive pulse at time t2. This pulse used to turn on solid-state switch and reset integrator circuit to zero.

Davis, W. T.↗

Battery test expert systems

The characteristics of NIHBES (nickel-hydrogen battery expert system) are described, with attention also given to NICBES-2 (nickel-cadmium battery expert system-2). The nickel-hydrogen battery testbed is set up almost identically to the nickel-cadmium battery testbed, with the exceptions of no battery protection and reconditioning circuits (BPRCs) and the frequency of transmission of data. The Ni-H2 testbed has no BPRCs and the data are transmitted every 30 s instead of every minute. An expert system shell was chosen to develop this particular expert system. The GoldWorks expert system shell from Gold Hill Computers was chosen for the task. NIHBES will extract the desired data and return fault diagnosis, status and advice, and decision support. Expert systems have been proven to be viable tools in the control and monitoring of space power systems. Presently, the DDAS (digital data acquisition system) monitors and controls the orbit time, and is responsible for limit checking, data acquisition, and data summaries. It is concluded that in the future control of the Hubble Space Telescope breadboard will be passed to NIHBES. NIHBES will be more beneficial to the testbed than the DDAS alone due to the limitations of the DDAS. The DDAS cannot provide long-term trend analysis, plotting capability, fault diagnosis, or advice.

Johnson, Yvette B.↗

Higher Order Parametric Excitation Modes for Spaceborne Quadrupole Mass Spectrometers

This paper describes a technique to significantly improve upon the mass peak shape and mass resolution of spaceborne quadrupole mass spectrometers (QMSs) through higher order auxiliary excitation of the quadrupole field. Using a novel multiresonant tank circuit, additional frequency components can be used to drive modulating voltages on the quadrupole rods in a practical manner, suitable for both improved commercial applications and spaceflight instruments. Auxiliary excitation at frequencies near twice that of the fundamental quadrupole RF frequency provides the advantages of previously studied parametric excitation techniques, but with the added benefit of increased sensed excitation amplitude dynamic range and the ability to operate voltage scan lines through the center of upper stability islands. Using a field programmable gate array, the amplitudes and frequencies of all QMS signals are digitally generated and managed, providing a robust and stable voltage control system. These techniques are experimentally verified through an interface with a commercial Pfeiffer QMG422 quadrupole rod system.When operating through the center of a stability island formed from higher order auxiliary excitation, approximately 50% and 400% improvements in 1% mass resolution and peak stability were measured, respectively, when compared with traditional QMS operation. Although tested with a circular rod system, the presented techniques have the potential to improve the performance of both circular and hyperbolic rod geometry QMS sensors.

Gershman, D. J.↗

A simulation analysis of phase processing circuitry in the Ohio University Omega receiver prototype

A FORTRAN IV simulation study of the all-digital phase-processing circuitry is described. A digital phase-lock loop (DPLL) forms the heart of the Omega navigation receiver prototype, and through the DPLL, the phase of the 10.2 KHz Omega signal was estimated when the true signal phase is contaminated with noise. The DPLL uses a frequency synthesizer as the reference oscillator. The synthesizer is composed of synchronous rate multipliers (SRM's) driven by a temperature-compensated crystal oscillator, and the use of the SRM's in this application introduces phase jitter which degrades system performance. Simulation of the frequency synthesizer discussed was to analyze the circuits on a bit-by-bit level in order to evaluate the overall design, to see easily the effects of proposed design changes prior to actual breadboarding, to determine the optimum integration time for the DPLL in an environment typical of general aviation conditions, and to quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.

Palkovic, R. A.↗

Single-Chip FPGA Azimuth Pre-Filter for SAR

A field-programmable gate array (FPGA) on a single lightweight, low-power integrated-circuit chip has been developed to implement an azimuth pre-filter (AzPF) for a synthetic-aperture radar (SAR) system. The AzPF is needed to enable more efficient use of data-transmission and data-processing resources: In broad terms, the AzPF reduces the volume of SAR data by effectively reducing the azimuth resolution, without loss of range resolution, during times when end users are willing to accept lower azimuth resolution as the price of rapid access to SAR imagery. The data-reduction factor is selectable at a decimation factor, M, of 2, 4, 8, 16, or 32 so that users can trade resolution against processing and transmission delays. In principle, azimuth filtering could be performed in the frequency domain by use of fast-Fourier-transform processors. However, in the AzPF, azimuth filtering is performed in the time domain by use of finite-impulse-response filters. The reason for choosing the time-domain approach over the frequency-domain approach is that the time-domain approach demands less memory and a lower memory-access rate. The AzPF operates on the raw digitized SAR data. The AzPF includes a digital in-phase/quadrature (I/Q) demodulator. In general, an I/Q demodulator effects a complex down-conversion of its input signal followed by low-pass filtering, which eliminates undesired sidebands. In the AzPF case, the I/Q demodulator takes offset video range echo data to the complex baseband domain, ensuring preservation of signal phase through the azimuth pre-filtering process. In general, in an SAR I/Q demodulator, the intermediate frequency (fI) is chosen to be a quarter of the range-sampling frequency and the pulse-repetition frequency (fPR) is chosen to be a multiple of fI. The AzPF also includes a polyphase spatial-domain pre-filter comprising four weighted integrate-and-dump filters with programmable decimation factors and overlapping phases. To prevent aliasing of signals, the bandwidth of the AzPF is made 80 percent of fPR/M. The choice of four as the number of overlapping phases is justified by prior research in which it was shown that a filter of length 4M can effect an acceptable transfer function. The figure depicts prototype hardware comprising the AzPF and ancillary electronic circuits. The hardware was found to satisfy performance requirements in real-time tests at a sampling rate of 100 MHz.

Gudim, Mimi↗

Understanding the Phase of Responsivity and Noise Sources in Frequency-Domain Multiplexed Readout of Transition Edge Sensor Bolometers

Abstract Cosmic microwave background (CMB) experiments have deployed focal planes with $$\mathcal {O}(10^{4})$$ O ( 10 4 ) transition edge sensor (TES) bolometers cooled to sub-Kelvin temperatures by multiplexing the readout of many TES channels onto a single pair of wires. Digital Frequency-domain Multiplexing (DfMux) is a multiplexing technique used in many CMB polarization experiments, such as the Simons Array, SPT-3 G, and EBEX. The DfMux system studied here uses LC filters with resonant frequencies ranging from 1.5 to 4.5 MHz connected to an array of TESs. Each detector has an amplitude-modulated carrier tone at the resonant frequency of its accompanying LC resonator. The signal is recovered via quadrature demodulation where the in-phase (I) component of the demodulated current is in phase with the complex admittance of the circuit and the quadrature (Q) component is orthogonal to I. Observed excess current noise in the Q component is consistent with fluctuations in the resonant frequency. This noise has been shown to be non-orthogonal to the phase of the detector’s responsivity. We present a detailed analysis of the phase of responsivity of the TES and noise sources in our DfMux readout system. Further, we investigate how modifications to the TES operating resistance and bias frequency can affect the phase of noise relative to the phase of the detector responsivity, using data from Simons Array to evaluate our predictions. We find that both the phase of responsivity and phase of noise are functions of the two tuning parameters, which can be purposefully selected to maximize signal-to-noise (SNR) ratio.

47 OTHER INSTRUMENTATION↗

Studies in optical parallel processing

Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.

Lee, S. H.↗

Crush Test Abuse Stand

The purpose of this system is to simulate an internal short on battery cells by causing deformation (a crushing force) in a cell without penetration. This is performed by activating a hydraulic cylinder on one side of a blast wall with a hydraulic pump located on the other. The operator can control the rate of the crush by monitoring a local pressure gauge connected to the hydraulic cylinder or a load cell digital display located at the hydraulic pump control area. The internal short simulated would be considered a worst-case scenario of a manufacturer fs defect. This is a catastrophic failure of a cell and could be a very destructive event. Fully charged cells are to have an internal short simulated at the center of the length of the cell (away from terminals). The crush can be performed with a .- to 1-in. (.0.6- to 2.5-cm) rod placed crossways to the cell axis, causing deformation of the cell without penetration. The OCV (open-circuit voltage) and temperature of the cells, as well as the pressure and crushing force, are recorded during the operation. Occurrence of an internal short accompanied by any visible physical changes such as venting, fires, or explosions is reported. Typical analytical data examined after the test would be plots of voltage, temperature, and pressure or force versus time. The rate of crushing force can be increased or decreased based on how fast the operator pumps the hydraulic pump. The size of cylinder used to compress the battery cell can be easily changed by adding larger or smaller fittings onto the end of the hydraulic cylinder based on the battery/cell size being tested. The cell is crushed remotely and videotaped, allowing the operator to closely monitor the situation from a safe distance.

Collins, Jacob↗

Synthesis algorithm of VLSI multipliers for ASIC

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

Chua, O. H.↗

Data Transfer for Multiple Sensor Networks Over a Broad Temperature Range

At extreme temperatures, cryogenic and over 300 C, few electronic components are available to support intelligent data transfer over a common, linear combining medium. This innovation allows many sensors to operate on the same wire bus (or on the same airwaves or optical channel: any linearly combining medium), transmitting simultaneously, but individually recoverable at a node in a cooler part of the test area. This innovation has been demonstrated using room-temperature silicon microcircuits as proxy. The microcircuits have analog functionality comparable to componentry designed using silicon carbide. Given a common, linearly combining medium, multiple sending units may transmit information simultaneously. A listening node, using various techniques, can pick out the signal from a single sender, if it has unique qualities, e.g. a voice. The problem being solved is commonly referred to as the cocktail party problem. The human brain uses the cocktail party effect when it is able to recognize and follow a single conversation in a party full of talkers and other noise sources. High-temperature sensors have been used in silicon carbide electronic oscillator circuits. The frequency of the oscillator changes as a function of the changes in the sensed parameter, such as pressure. This change is analogous to changes in the pitch of a person s voice. The output of this oscillator and many others may be superimposed onto a single medium. This medium may be the power lines supplying current to the sensors, a third wire dedicated to data transmission, the airwaves through radio transmission, an optical medium, etc. However, with nothing to distinguish the identities of each source that is, the source separation this system is useless. Using digital electronic functions, unique codes or patterns are created and used to modulate the output of the sensor.

Krasowski, Michael↗

Numerical and experimental analysis of mechanically induced failure in electric vehicle battery modules

Mitigating thermal runaway and cell-to-cell propagation is essential for improving the safety of electric and hybrid vehicles. Enhancing digital twin capabilities to predict battery mechanical abuse is particularly critical for automotive and aerospace applications, where crashworthiness is a key concern. Understanding failure conditions and propagation in battery modules during mechanical abuse is complex due to interactions between structural deformation, heat transfer, electrochemical processes, exothermic reactions and mechanical fracture. While prior studies have focused on modeling cell-level behavior, extending these models to module or pack level is necessary for a system level understating of electric vehicle safety. This study develops coupled large deformation finite element models that simultaneously solve for electrochemistry, material failure, internal short circuit and thermal runaway propagation. The models account for mechanical and thermal interactions between lithium-ion cells and other battery components while the contact interfaces are evolving with time. Model-predicted voltage, temperature and force responses are compared with experimental data for validation. The results demonstrate that the approach captures key failure mechanisms, including thermal propagation through heat transfer, electrical propagation from short circuits in parallel-connected cells, and mechanical propagation via penetration and crack formation. These findings show that computational models are valuable tools for understanding battery module failure and providing insight that can reduce the need for extensive experimental testing.

25 ENERGY STORAGE↗

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗