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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Breadboard design and production units of integrated static inverter
Instability, high threshold voltage, and gamma radiation in MOS transistors
Cardiovascular reflex conditioning system to provide periodic inflation of pneumatic cuffs to minimize prolonged weightlessness effects on astronauts
Breadboard model development of integrated static inverter
Material and processing development, magnetic storage devices, and design of memory incorporating foil storage device
Flip-flop arrays, power transistors, epitaxial stress, and other technological developments in integrated static inverter program
Ammonia fueled resistojet thrustor system for three-axis attitude control and two-direction station-keeping of stable platform type satellite
Circuitry, fabrication, and performance characteristics of 75-VA integrated static inverter for gyro platform power supply
Development, fabrication, and evaluation of neodymium doped YAG laser rods
Design, development, and fabrication of fluidic accelerometers
Monolithic amplifier incorporating vertical n-p-n and lateral p-n-p transistor structures
Design optimization and production of fluidic accelerometer for angular rate measurements
Development and fabrication of filament composite nondestructive test standards
Integrally woven quartz fiber I beam with uniform thickness using epoxy resin
The technology status and problem areas which exist for the application of flat conductor cabling to solar cell arrays are summarized. Details covering the design, connector manufacture, and prototype test results are also summarized.
Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.
The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.
Details of the fabrication and assembly of two 99 cm by 99 cm (39 in. by 39 in.) beryllium heat shield test panels are presented. Each panel consists of two hat-stiffened, formed skins which overlap a transverse slip joint at the center of the panel; clips join the two skins at the slip joint, and continuous standoffs are provided at the ends of the panel. The hat-stiffeners are joined to the skin by furnace-brazing, using the braze alloy BAg 18. The parts are generally 0.051 cm (0.020 in.) thick. Tools used to form the detail parts are shown, together with the results of preliminary forming and brazing trials to verify processing techniques. Problems encountered in the manufacture of the panels are discussed.