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At least 1,081 records · Page 60
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Bunch Shaping in Electron Linear Accelerators

Modern electron linear accelerators are often designed to produce smooth bunch distributions characterized by their macroscopic ensemble-average moments. However, an increasing number of accelerator applications call for finer control over the beam distribution, such as by requiring specific shapes for its projection along one coordinate. Ultimately, the control of the beam distribution at the single-particle level could enable new opportunities in accelerator science. This review discusses the recent progress toward controlling electron beam distributions on the “mesoscopic” scale with an emphasis on shaping the beam or introducing complex correlations required for some applications. This review emphasizes experimental and theoretical developments of electron-bunch shaping methods based on bounded external electromagnetic fields or via interactions with the self-generated velocity and radiation fields.

Ha, G.↗
DOE OSTI2025

Greater than 1000-fold Gain in a Free-Electron Laser Driven by a Laser-Plasma Accelerator with High Reliability

Compact free-electron lasers (FELs) based on plasma-based accelerators have been envisioned for many years. While recent milestone experiments have demonstrated feasibility, further progress is needed to establish laser-plasma-accelerator-driven FELs as reliable light sources. Demonstrating both full FEL saturation and reliable operation commensurate with conventional FEL facilities is critical. We report progress on both of these fronts. FEL gain exceeding 1000 at a wavelength of 420 nm in the self-amplified spontaneous emission regime has been measured. Lower and upper bounds for the characteristic exponential gain length were measured at 16.7-22.5 cm. Additionally, reliability of the laser-plasma-accelerator-driven FEL, defined here as the percentage of shots displaying FEL gain, reached an unprecedented level of greater than 90% over the course of an hour while operating at 1 Hz repetition rate.

Barber, S K↗
DOE OSTI2022

H-GCN: A Graph Convolutional Network Accelerator on Versal ACAP Architecture

Recently Graph Neural Networks (GNNs) have drawn tremendous attentions due to their unique capability to extend the Machine Learning (ML) approaches to broadly defined applications with unstructured data, especially graphs. Comparing with other ML modalities, the acceleration of GNNs is as critical but even more challenging due to the irregularity and heterogeneity from graph typologies that together limit the performance. Existing efforts mainly focus on handling graphs’ irregularity, however, have not studied the heterogeneity. To this end, in this work, we propose H-GCN, a PL-AIE-based hybrid accelerator that leverages the emerging heterogeneity of Xilinx Versal ACAPs to achieve high-performance GNN inference. In particular, H-GCN partitions each graph into three subgraphs based on its inherent heterogeneity and processes them using PL and the newly emerged AIE respectively. To further improve the performance, we explore the sparsity support of AIE and develop an efficient density-aware method to map tiles of SpMM onto the systolic tensor array automatically. Compared with the current state-of-the-art GCN accelerator, HGCN achieves on average 1.5× speedups.

Zhang, Chengming↗
DOE OSTI2021

A Survey: Handling Irregularities in Neural Network Acceleration with FPGAs

In the last decade, Artificial Intelligence (AI) through Deep Neural Networks (DNNs) has penetrated virtually every aspect of science, technology, and business. Many types of DNNs have been and continue to be developed, including Convolutional Neural Networks (CNNs), Recurrent Neural Net- works (RNNs), and Graph Neural Networks (GNNs). The overall problem for all of these Neural Networks (NNs) is that their target applications generally pose stringent constraints on latency and throughput, while also having strict accuracy requirements. There have been many previous efforts in creating hardware to accelerate NNs. The problem designers face is that optimal NN models typically have significant irregularities, making them hardware-unfriendly. In this paper, we first define the problems in NN acceleration by characterizing common irregularities in NN processing into 4 types; then we summarize the existing works that handle the four types of irregularities efficiently using hardware, especially FPGAs; finally, we provide a new vision of next-generation FPGA-based NN acceleration: that the emerging heterogeneity in the next-generation FPGAs is the key to achieving higher performance.

Geng, Tong↗
DOE OSTI2021

Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators

The growing numbers of application areas for artificial intelligence (AI) methods have led to an explosion of domain-specific accelerators that could support every new machine learning (ML) algorithm advancement, clearly highlighting the need for a capability to quickly and automatically transition from algorithm definition to hardware implementation and explore design space along a variety of SWaP (size, weight and Power). The software defined architectures (SODA) synthesizer implements a compiler-based modular infrastructure for the end-to-end generation of machine learning accelerators from high-level frameworks to hardware description language. At the same time, neuromorphic computing, by mimicking how the brain operates, promises to perform artificial intelligence tasks at efficiencies orders of magnitude higher than the current conventional tensor-processing based accelerators, as demonstrated by a variety of specialized designs leveraging Spiking Neural Networks (SNNs). Nevertheless, the mapping of an artificial neural network (ANN) to solutions supporting SNNs is still a non-trivial and very device-specific task, and completely lack the possibility to design hybrid systems that integrate conventional and spiking neural models. In this paper we discuss the support for such an integrated generation leveraging the SODA Synthesizer framework and its modular structure. In particular, we present a new MLIR dialect (part of the SODA frontend) that allows expressing spiking neural network features (e.g., available resources, spiking sequences, analog signal reading, etc.) and illustrate how it enables mapping to Spiking Neurons and deployment to the related specialized hardware (which, in the digital domain, could be generated through the other existing layers of the SODA Synthesizer). We then discuss the opportunities for even deeper integration afforded by the hardware compilation infrastructure, providing a path towards the generation of complex heterogeneous artificial intelligence systems.

Curzel, Serena↗
DOE OSTI2021

Optimizing FPGA-based Accelerator Design for Large-Scale Molecular Similarity Search (Special Session Paper)

Molecular similarity search has been widely used in drug discovery to rapidly identify structurally similar compounds from large molecular databases. With the increasing size of chemical libraries, there is growing interest in the efficient ac- celeration of large-scale similarity search. Existing works mainly focus on CPU and GPU to accelerate the computation of Tatimoto coefficient in measuring the pairwise similarity between different molecular fingerprints. In this paper, we propose and optimize an FPGA-based accelerator design on exhaustive and approximate search algorithms. On exhaustive search using BitBound & fold- ing, we analyze the similarity cutoff and folding level relationship with search speedup and accuracy, and propose a scalable on- the-fly query engine on FPGAs to reduce the resource utilization and pipeline interval. We achieve a 450 million compounds-per- second processing throughput for a single query engine. On approximate search using hierarchical navigable small world (HNSW), a popular algorithm with high recall and query speed, we propose an FPGA-based graph traversal engine to utilize high throughput register array based priority queue and fine- grained distance calculation engine to increase the processing capability. Experimental results show that the proposed FPGA- based HNSW implementation achieves a 35× speedup than existing works on CPU. To the best of our knowledge, our FPGA- based implementation is the first attempt to accelerate molecular similarity search on FPGA and has the highest performance among existing approaches.

Peng, Hongwu↗
DOE OSTI2024

Accelerating Lossy and Lossless Compression on Emerging BlueField DPU Architectures

Data compression has become a crucial technique in addressing performance bottlenecks caused by increasing data volumes in High-Performance Computing (HPC), Big Data, and Deep Learning (DL). Despite its potential to boost system performance, recent studies have identified significant challenges with existing compression methods, mainly due to their high computational demands amidst continuously growing data sizes. Concurrently, the advent of Data Processing Units (DPUs), equipped with programmable System-on-Chip (SoC) and specialized compression accelerators, offers a promising opportunity to alter the landscape of data compression. This paper explores the complexities and potential of leveraging NVIDIA BlueField DPUs to accelerate lossy and lossless compression. Towards this, we introduce PEDAL, an innovative library that leverages the hardware capabilities of DPUs to unify and optimize data compression designs. Moreover, we seamlessly co-design PEDAL with the popular MPICH MPI library, demonstrating up to 101x speedup in compression time and 88x decrease in communication latency. Drawing on these achievements, we share our experience with various research communities about accelerating data compression on DPUs in communication-oriented HPC scenarios.

Li, Yuke↗
DOE OSTI2023

Conceptual Design of a 20 T Hybrid Cos-Theta Dipole Superconducting Magnet for Future High-Energy Particle Accelerators

High energy physics research will need more and more powerful circular accelerators in the next decades. It is therefore desirable to have dipole magnets able to produce the largest possible magnetic field, in order to keep the machine diameter within a reasonable size. A 20 T dipole is considered a desired achievement since it would allow the construction of an 80 km machine, able to circulate 100 TeV proton beams. In order to reach 20 T, a hybrid Low-Temperature Superconductor (LTS) - High-Temperature Superconductor (HTS) magnet is needed, since LTS technology is presently limited to ~16 T for accelerator magnet applications. In this paper, we present the design of a 6 layers 20 T hybrid dipole magnet using Nb 3 Sn (LTS) and Bi2212 (HTS). Here we show that it is possible to achieve this magnetic field with accelerator field quality, with sufficient margin on a realistic conductor, keeping the stresses within safe limit, avoiding conductor degradation.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Deep Multitask Learning Models for Radiation Estimation at High Energy Accelerator Facility

Controlling the dose of radiation exposure in potential radioactive facilities is critical for ensuring the safety of staff and the public. Here, in this paper, we developed machine learning models to estimate radiation exposure efficiently at the Thomas Jefferson National Accelerator Facility (JLab), aiming to enhance safety in both accelerator facilities and public areas. Multiple sensors were deployed around the three experimental halls at JLab. Data on single-beam currents, energy levels, and radiation values at the sensor locations were collected during accelerator operation. We proposed a multi-task learning model for radiation estimation, utilizing either one-dimensional convolutional neural networks (1-D CNNs) or long short-term memory networks (LSTMs) as the backbone. The proposed model was trained to simultaneously estimate radiation levels at the sensor locations. Experimental results demonstrated that the proposed model with LSTM backbone achieved the best estimation performance, with an average R 2 score of 0.7557 for estimation within the same year and 0.7157 for estimation across different years. These results significantly surpassed those of competing models.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Calibration of CDM-Based Creep Constitutive Model Using Accelerated Creep Test (ACT) Data

In conventional creep testing (CCT) a specimen is subject to constant load and temperature for a long-duration until creep rupture occurs. Conventional testing can be costly when considering the number of experiments needed to characterize the creep response of a material over a range of stress and temperature. To predict long-term creep-rupture properties, the time-temperature-stress superposition principle (TTSSP) approach has been employed where stress and/or temperature is applied at an elevated level; the result of which are extrapolated down to low stress and/or temperature conditions. These methods have been successful in predicting minimum-creep-strain-rate (MCSR) and stress-rupture (SR) but suffer from an inability to predict the creep deformation curve or account for changes in deformation mechanisms or aging that occurs at long-duration. An accelerated technique, termed the Stepped isostress method (SSM) allows the accelerated testing of materials to determine their creep deformation response. Unlike TTSSP tests, the SSM test employs a single specimen where the stress is periodically step increased until rupture. The SSM creep deformation curve is processed (time and strain shifted) to produce an accelerated creep deformation curve that represent the creep deformation curve at the initial stress level in SSM. A processing procedure for metals has yet to be developed. The research objective of this study is to develop a processing procedure for SSM test data using a creep-damage constitutive model. Triplicate SSM tests were conducted on Ni-based superalloy Inconel 718 at 650°C with stress being periodically increased until rupture. Triplicate CCT tests were conducted at the initial stress level of the SSM tests. The Sine-hyperbolic (Sinh) creep-damage model was employed in this study. The Sinh creep-damage constitutive model is based on coupled creep strain rate and damage evolution equations; where both rates are dependent on the current state of damage. Calibration is two-step: analytical and numerical optimization. Each stepped creep deformation curve is tackled quasi-analytically to determine MCSR and SR related material constants and accumulated damage. The damage accumulated at the end of each step was then passed onto subsequent steps to calibrate the MCSR, rupture prediction, and damage evolution. Numerical optimization was applied to optimize model constants involved in the creep strain constitutive equations in order to generate best-fitted Sinh creep deformation curves. The Sinh model predictions were compared to the SSM and CCT data. The Sinh model satisfactorily predicts the SSM data and thus the calibrated material constants provides a good estimate of rupture found in the CCT data. Calibration using SSM data reduces the number of tests needed to calibrate a model; significantly reducing costs. A single SSM test replaces numerous creep tests at different stresses.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Accelerated aging of all-inorganic, interface-stabilized perovskite solar cells

To understand degradation routes and improve the stability of perovskite solar cells (PSCs), accelerated aging tests are needed. Here, we use elevated temperatures (up to 110°C) to quantify the accelerated degradation of encapsulated CsPbI 3 PSCs under constant illumination. Incorporating a two-dimensional (2D) Cs 2 PbI 2 Cl 2 capping layer between the perovskite active layer and hole-transport layer stabilizes the interface while increasing power conversion efficiency of the all-inorganic PSCs from 14.9 to 17.4%. Devices with this 2D capping layer did not degrade at 35°C and required >2100 hours at 110°C under constant illumination to degrade by 20% of their initial efficiency. Degradation acceleration factors based on the observed Arrhenius temperature dependence predict intrinsic lifetimes of 51,000 ± 7000 hours (>5 years) operating continuously at 35°C.

Science & Technology - Other Topics↗
DOE OSTI2020

Accelerating Scientific Computing in the Post-Moore’s Era

Novel uses of graphical processing units for accelerated computation revolutionized the field of high-performance scientific computing by providing specialized workflows tailored to algorithmic requirements. As the era of Moore’s law draws to a close, many new non–von Neumann processors are emerging as potential computational accelerators, including those based on the principles of neuromorphic computing, tensor algebra, and quantum information. While development of these new processors is continuing to mature, the potential impact on accelerated computing is anticipated to be profound. We discuss how different processing models can advance computing in key scientific paradigms: machine learning and constraint satisfaction. Significantly, each of these new processor types utilizes a fundamentally different model of computation, and this raises questions about how to best use such processors in the design and implementation of applications. While many processors are being developed with a specific domain target, the ubiquity of spin-glass models and neural networks provides an avenue for multi-functional applications. Furthermore, this also hints at the infrastructure needed to integrate next-generation processing units into future high-performance computing systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

FLASH: FPGA-Accelerated Smart Switches with GCN Case Study

Some communication switches, e.g., the Mellanox SHArP and those in the IBM BlueGene clusters, are augmented to process packets at the application level with fixed-function collectives. This approach, however, lacks flexibility, which limits their applicability in diverse and dynamic workloads. Recently, a new type of programmable packet processor, which uses high-level languages, e.g., P4, has emerged as possible candidates. P4-based switches, however, fall short in certain applications, including machine learning, where capabilities not currently supported by P4 are needed. These include more complex calculation, such as sparse computation and fused multiply-accumulate, data-intensive floating point operations, data reuse, and significant memory. The problem addressed here is that such a switch augmentation needs to support: a large amount of state, significant flexible compute capability, and ease of programming, all while maintaining full functionality, including ensuring high throughput, and demonstrating utility. In this work, we propose a programmable look-aside-type accelerator that can be embedded into, or attached to, existing communication switch pipelines and that is capable of processing packets at line-rate. The proposed in-switch accelerator is based on mixing an ISA (subset of RISC-V instructions) with dataflow graphs (found in CGRAs). To augment performance, vector instructions are also supported. To facilitate usability, we have developed a complete toolchain to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator. While this approach is flexible enough to support various workloads, in this paper, we consider Graph Convolutional Networks (GCNs) as a case study. Experimental results show that this approach considerably improves the performance of distributed GCN applications.

Haghi, Pouya↗
DOE OSTI2023

Application Experiences on a GPU-Accelerated Arm-based HPC Testbed

This paper assesses and reports the experience of ten teams working to port, validate, and benchmark several High Performance Computing applications on a novel GPU-accelerated Arm testbed system. The testbed consists of eight NVIDIA Arm HPC Developer Kit systems, each one equipped with a server-class Arm CPU from Ampere Computing and two data center GPUs from NVIDIA Corp. The systems are connected together using InfiniBand interconnect. The selected applications and mini-apps are written using several programming languages and use multiple accelerator-based programming models for GPUs such as CUDA, OpenACC, and OpenMP offloading. Working on application porting requires a robust and easy-to-access programming environment, including a variety of compilers and optimized scientific libraries. The goal of this work is to evaluate platform readiness and assess the effort required from developers to deploy well-established scientific workloads on current and future generation Arm-based GPU-accelerated HPC systems. The reported case studies demonstrate that the current level of maturity and diversity of software and tools is already adequate for large-scale production deployments.

Elwasif, Wael↗
DOE OSTI2024

SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators

This article presents a methodology for the Synthesis of PARallel multi-Threaded Accelerators (SPARTA) from OpenMP annotated C/C++ specifications. SPARTA extends an open-source HLS tool, enabling the generation of accelerators that provide latency tolerance for irregular memory accesses through multithreading, support fine-grained memory-level parallelism through a hot-potato deflection-based network-on-chip (NoC), support synchronization constructs, and can instantiate memory-side caches. Our approach is based on a custom runtime OpenMP library, providing flexibility and extensibility. Experimental results show high scalability when synthesizing irregular graph kernels. The accelerators generated with our approach are, on average, 2.29x faster than state-of-the-art HLS methodologies.

Design automation↗
DOE OSTI2025

TorchBraid: High-Performance Layer-Parallel Training of Deep Neural Networks with MPI and GPU Acceleration

TorchBraid is a high-performance implementation of layer-parallel training for deep neural networks (DNNs) supporting MPI-based parallelism and GPU acceleration. Layer-parallel training has been developed to overcome the serialization inherent in forward and backward propagation of DNNs that limits utilization of computational resources in the strong scaling limit. To achieve this, TorchBraid integrates the PyTorch neural network framework with the state-of-the-art XBraid time-parallel library. Furthermore, this article presents the use and performance of TorchBraid, in addition to solutions for overcoming the algorithmic challenges inherent in combining automatic differentiation with layer-parallel. Results are presented with and without GPU acceleration for the Tiny ImageNet and MNIST image classification data sets, as well as recurrent neural networks. Overall, TorchBraid enables fast training of DNNs, both in a strong and weak scaling context. In addition to the TorchBraid software, several new advances in applying layer-parallel algorithms are detailed. Integration of layer-parallel with data-parallel algorithms is presented for the first time, showing the computational advantages of the combination. Standard deep learning techniques, like batch-normalization, are developed for layer-parallel training. Finally, a new approach combining layer-parallel with spatial coarsening in order to accelerate training for 3D image classification shows roughly a 10× speedup over serial execution.

Layer-parallel↗
DOE OSTI2020

Toward fusion plasma scenario planning for NSTX-U using machine-learning-accelerated models

One of the most promising devices for realizing power production through nuclear fusion is the tokamak. To maximize performance, it is preferable that tokamak reactors achieve advanced operating scenarios characterized by good plasma confinement, improved magnetohydrodynamic (MHD) stability, and a largely non-inductively driven plasma current. Such scenarios could enable steady-state reactor operation with high \emph{fusion gain} --- the ratio of produced fusion power to the external power provided through the plasma boundary. Precise and robust control of the evolution of the plasma boundary shape as well as the spatial distribution of the plasma current, density, temperature, and rotation will be essential to achieving and maintaining such scenarios. The complexity of the evolution of tokamak plasmas, arising due to nonlinearities and coupling between various parameters, motivates the use of model-based control algorithms that can account for the system dynamics. In this work, a learning-based accelerated model trained on data from the National Spherical Torus Experiment Upgrade (NSTX-U) is employed to develop planning and control strategies for regulating the density and temperature profile evolution around desired trajectories. The proposed model combines empirical scaling laws developed across multiple devices with neural networks trained on empirical data from NSTX-U and a database of first-principles-based computationally intensive simulations. The reduced execution time of the accelerated model will enable practical application of optimization algorithms and reinforcement learning approaches for scenario planning and control development. An initial demonstration of applying optimization approaches to the learning-based model is presented, including a strategy for mitigating the effect of leaving the finite validity range of the accelerated model. The approach shows promise for actuator planning between experiments and in real-time.

machine learning↗
DOE OSTI2024

FTTN: Feature-Targeted Testing for Numerical Properties of NVIDIA & AMD Matrix Accelerators

FTTN is a test suite to evaluate the numerical behaviors of matrix accelerators of GPUs (NVIDIA Tensor Cores and AMD Matrix Cores) in a quick and simple setting. Matrix accelerators are heavily used in today's computationally intense applications to speed up matrix multiplications. This test suite provides a comprehensive study on the numerical behaviors of these accelerators, including support for subnormals, rounding modes, extra precision bits and FMA features. Is there

Laguna Peralta, Ignacio↗