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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,081 records · Page 60
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Modeling of anisotropic two-dimensional materials monolayer HfS{sub 2} and phosphorene metal-oxide semiconductor field effect transistors

Ballistic transport characteristics of metal-oxide semiconductor field effect transistors (MOSFETs) based on anisotropic two-dimensional materials monolayer HfS{sub 2} and phosphorene are explored through quantum transport simulations. We focus on the effects of the channel crystal orientation and the channel length scaling on device performances. Especially, the role of degenerate conduction band (CB) valleys in monolayer HfS{sub 2} is comprehensively analyzed. Benchmarking monolayer HfS{sub 2} with phosphorene MOSFETs, we predict that the effect of channel orientation on device performances is much weaker in monolayer HfS{sub 2} than in phosphorene due to the degenerate CB valleys of monolayer HfS{sub 2}. Our simulations also reveal that at 10 nm channel length scale, phosphorene MOSFETs outperform monolayer HfS{sub 2} MOSFETs in terms of the on-state current. However, it is observed that monolayer HfS{sub 2} MOSFETs may offer comparable, but a little bit degraded, device performances as compared with phosphorene MOSFETs at 5 nm channel length.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In{sub 1−x}Ga{sub x}As channel capping layer

In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor) devices with a channel capping layer. The impacts of thickness and gallium (Ga) concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In{sub 1−x}Ga{sub x}As/In{sub 0.53}Ga{sub 0.47}As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In{sub 0.68}Ga{sub 0.32}As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF) resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85{sup o} is needed for the device with an averaged grain size of NiSi below 4x4 nm{sup 2}.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Phosphorus and boron diffusion paths in polycrystalline silicon gate of a trench-type three-dimensional metal-oxide-semiconductor field effect transistor investigated by atom probe tomography

The dopant (P and B) diffusion path in n- and p-types polycrystalline-Si gates of trench-type three-dimensional (3D) metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated using atom probe tomography, based on the annealing time dependence of the dopant distribution at 900 °C. Remarkable differences were observed between P and B diffusion behavior. In the initial stage of diffusion, P atoms diffuse into deeper regions from the implanted region along grain boundaries in the n-type polycrystalline-Si gate. With longer annealing times, segregation of P on the grain boundaries was observed; however, few P atoms were observed within the large grains or on the gate/gate oxide interface distant from grain boundaries. These results indicate that P atoms diffuse along grain boundaries much faster than through the bulk or along the gate/gate oxide interface. On the other hand, in the p-type polycrystalline-Si gate, segregation of B was observed only at the initial stage of diffusion. After further annealing, the B atoms became uniformly distributed, and no clear segregation of B was observed. Therefore, B atoms diffuse not only along the grain boundary but also through the bulk. Furthermore, B atoms diffused deeper than P atoms along the grain boundaries under the same annealing conditions. This information on the diffusion behavior of P and B is essential for optimizing annealing conditions in order to control the P and B distributions in the polycrystalline-Si gates of trench-type 3D MOSFETs.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2015

Solution-grown small-molecule organic semiconductor with enhanced crystal alignment and areal coverage for organic thin film transistors

Drop casting of small-molecule organic semiconductors typically forms crystals with random orientation and poor areal coverage, which leads to significant performance variations of organic thin-film transistors (OTFTs). In this study, we utilize the controlled evaporative self-assembly (CESA) method combined with binary solvent system to control the crystal growth. A small-molecule organic semiconductor,2,5-Di-(2-ethylhexyl)-3,6-bis(5"-n-hexyl-2,2',5',2"]terthiophen-5-yl)-pyrrolo[3,4-c]pyrrole-1,4-dione (SMDPPEH), is used as an example to demonstrate the effectiveness of our approach. By optimizing the double solvent ratios, well-aligned SMDPPEH crystals with significantly improved areal coverage were achieved. As a result, the SMDPPEH based OTFTs exhibit a mobility of 1.6 × 10 -2 cm 2 /V s, which is the highest mobility from SMDPPEH ever reported.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2015

Negative bias-and-temperature stress-assisted activation of oxygen-vacancy hole traps in 4H-silicon carbide metal-oxide-semiconductor field-effect transistors

We use hybrid-functional density functional theory-based Charge Transition Levels (CTLs) to study the electrical activity of near-interfacial oxygen vacancies located in the oxide side of 4H-Silicon Carbide (4H-SiC) power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Based on the “amorphousness” of their local atomic environment, oxygen vacancies are shown to introduce their CTLs either within (permanently electrically active) or outside of (electrically inactive) the 4H-SiC bandgap. The “permanently electrically active” centers are likely to cause threshold voltage (V{sub th}) instability at room temperature. On the other hand, we show that the “electrically inactive” defects could be transformed into various “electrically active” configurations under simultaneous application of negative bias and high temperature stresses. Based on this observation, we present a model for plausible oxygen vacancy defects that could be responsible for the recently observed excessive worsening of V{sub th} instability in 4H-SiC power MOSFETs under high temperature-and-gate bias stress. This model could also explain the recent electrically detected magnetic resonance observations in 4H-SiC MOSFETs.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2015

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

An alternative multi-frequency inversion-charge pumping (MFICP) technique was developed to directly separate the inversion charge density (N{sub inv}) from the trapped charge density in high-k/InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). This approach relies on the fitting of the frequency response of border traps, obtained from inversion-charge pumping measurements performed over a wide range of frequencies at room temperature on a single MOSFET, using a modified charge trapping model. The obtained model yielded the capture time constant and density of border traps located at energy levels aligned with the InGaAs conduction band. Moreover, the combination of MFICP and pulsed I{sub d}-V{sub g} measurements enabled an accurate effective mobility vs N{sub inv} extraction and analysis. The data obtained using the MFICP approach are consistent with the most recent reports on high-k/InGaAs.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2015

Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I{sub DS} by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I{sub DS} by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Ge{sub 0.83}Sn{sub 0.17} p-channel metal-oxide-semiconductor field-effect transistors: Impact of sulfur passivation on gate stack quality

The effect of room temperature sulfur passivation of the surface of Ge{sub 0.83}Sn{sub 0.17} prior to high-k dielectric (HfO{sub 2}) deposition is investigated. X-ray photoelectron spectroscopy (XPS) was used to examine the chemical bonding at the interface of HfO{sub 2} and Ge{sub 0.83}Sn{sub 0.17}. Sulfur passivation is found to be effective in suppressing the formation of both Ge oxides and Sn oxides. A comparison of XPS results for sulfur-passivated and non-passivated Ge{sub 0.83}Sn{sub 0.17} samples shows that sulfur passivation of the GeSn surface could also suppress the surface segregation of Sn atoms. In addition, sulfur passivation reduces the interface trap density D{sub it} at the high-k dielectric/Ge{sub 0.83}Sn{sub 0.17} interface from the valence band edge to the midgap of Ge{sub 0.83}Sn{sub 0.17}, as compared with a non-passivated control. The impact of the improved D{sub it} is demonstrated in Ge{sub 0.83}Sn{sub 0.17} p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs). Ge{sub 0.83}Sn{sub 0.17} p-MOSFETs with sulfur passivation show improved subthreshold swing S, intrinsic transconductance G{sub m,int}, and effective hole mobility μ{sub eff} as compared with the non-passivated control. At a high inversion carrier density N{sub inv} of 1 × 10{sup 13 }cm{sup −2}, sulfur passivation increases μ{sub eff} by 25% in Ge{sub 0.83}Sn{sub 0.17} p-MOSFETs.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Hole mobility modulation of solution-processed nickel oxide thin-film transistor based on high-k dielectric

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiO{sub x}) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiO{sub x} TFTs, together with the characteristics of NiO{sub x} thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al{sub 2}O{sub 3}) gate dielectric, the electrical performance of NiO{sub x} TFT was improved significantly compared with those based on SiO{sub 2} dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm{sup 2}/V s, which is mainly beneficial from the high areal capacitance of the Al{sub 2}O{sub 3} dielectric and high-quality NiO{sub x}/Al{sub 2}O{sub 3} interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{sup 11} cm{sup −2}).

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Auger generation as an intrinsic limit to tunneling field-effect transistor performance

Many in the microelectronics field view tunneling field-effect transistors (TFETs) as society's best hope for achieving a >10× power reduction for electronic devices; however, despite a decade of considerable worldwide research, experimental TFET results have significantly underperformed simulations and conventional MOSFETs. To explain the discrepancy between TFET experiments and simulations, we investigate the parasitic leakage current due to Auger generation, an intrinsic mechanism that cannot be mitigated with improved material quality or better device processing. We expose the intrinsic link between the Auger and band-to-band tunneling rates, highlighting the difficulty of increasing one without the other. From this link, we show that Auger generation imposes a fundamental limit on ultimate TFET performance.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Improving the radiation hardness of graphene field effect transistors

Ionizing radiation poses a significant challenge to the operation and reliability of conventional silicon-based devices. In this paper, we report the effects of gamma radiation on graphene field-effect transistors (GFETs), along with a method to mitigate those effects by developing a radiation-hardened version of our back-gated GFETs. We demonstrate that activated atmospheric oxygen from the gamma ray interaction with air damages the semiconductor device, and damage to the substrate contributes additional threshold voltage instability. Our radiation-hardened devices, which have protection against these two effects, exhibit minimal performance degradation, improved stability, and significantly reduced hysteresis after prolonged gamma radiation exposure. Finally, we believe this work provides an insight into graphene's interactions with ionizing radiation that could enable future graphene-based electronic devices to be used for space, military, and other radiation-sensitive applications.

36 MATERIALS SCIENCE↗
DOE OSTI2017

Increased mobility and on/off ratio in organic field-effect transistors using low-cost guanine-pentacene multilayers

Layer-by-layer deposited guanine and pentacene in organic field-effect transistors (OFETs) is introduced. Through adjusting the layer thickness ratio of guanine and pentacene, the tradeoff of two electronic parameters in OFETs, charge carrier mobility and current on/off ratio, was controlled. The charge mobility was enhanced by depositing pentacene over and between guanine layers and by increasing the proportion of pentacene in the layer-by-layer system, while the current on/off ratio was increased via the decreased off current induced by the guanine layers. The tunable device performance was mainly ascribed to the trap and dopant neutralizing properties of the guanine layers, which would decrease the density of free hydroxyl groups in the OFETs. Furthermore, the cost of the devices could be reduced remarkably via the adoption of low-cost guanine.

42 ENGINEERING↗
DOE OSTI2017

Moving towards the magnetoelectric graphene transistor

Here, the interfacial charge transfer between mechanically exfoliated few-layer graphene and Cr 2 O 3 (0001) surfaces has been investigated. Electrostatic force microscopy and Kelvin probe force microscopy studies point to hole doping of few-layer graphene, with up to a 150 meV shift in the Fermi level, an aspect that is confirmed by Raman spectroscopy. Density functional theory calculations furthermore confirm the p-type nature of the graphene/chromia interface and suggest that the chromia is able to induce a significant carrier spin polarization in the graphene layer. A large magnetoelectrically controlled magneto-resistance can therefore be anticipated in transistor structures based on this system, a finding important for developing graphene-based spintronic applications.

36 MATERIALS SCIENCE↗
DOE OSTI2018

Atomically engineered epitaxial anatase TiO 2 metal-semiconductor field-effect transistors

Here, anatase TiO 2 is a promising material for a vast array of electronic, energy, and environmental applications, including photocatalysis, photovoltaics, and sensors. A key requirement for these applications is the ability to modulate its electrical properties without dominant dopant scattering and while maintaining high carrier mobility. Here, we demonstrate the room temperature field-effect modulation of the conducting epitaxial interface between anatase TiO 2 and LaAlO 3 (001), which arises for LaO-terminated LaAlO 3 , while the AlO 2- terminated interface is insulating. This approach, together with the metal-semiconductor field-effect transistor geometry, naturally bypasses the gate/channel interface traps, resulting in a high field-effect mobility μ FE of 3.14 cm 2 (V s) –1 approaching 98% of the corresponding Hall mobility μ Hall . Accordingly, the channel conductivity is modulated over 6 orders of magnitude over a gate voltage range of ~4 V.

36 MATERIALS SCIENCE↗