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At least 1,081 records · Page 60
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Ultrafast jet classification at the HL-LHC

Abstract Three machine learning models are used to perform jet origin classification. These models are optimized for deployment on a field-programmable gate array device. In this context, we demonstrate how latency and resource consumption scale with the input size and choice of algorithm. Moreover, the models proposed here are designed to work on the type of data and under the foreseen conditions at the CERN large hadron collider during its high-luminosity phase. Through quantization-aware training and efficient synthetization for a specific field programmable gate array, we show that O ( 100 ) ns inference of complex architectures such as Deep Sets and Interaction Networks is feasible at a relatively low computational resource cost.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

SPIDERS: overview of the X-ray galaxy cluster follow-up and the final spectroscopic data release

ABSTRACT SPIDERS (The SPectroscopic IDentification of eROSITA Sources) is a large spectroscopic programme for X-ray selected galaxy clusters as part of the Sloan Digital Sky Survey-IV (SDSS-IV). We describe the final data set in the context of SDSS Data Release 16 (DR16): the survey overall characteristics, final targeting strategies, achieved completeness, and spectral quality, with special emphasis on its use as a galaxy cluster sample for cosmology applications. SPIDERS now consists of about 27 000 new optical spectra of galaxies selected within 4000 photometric red sequences, each associated with an X-ray source. The excellent spectrograph efficiency and a robust analysis pipeline yield a spectroscopic redshift measurement success rate exceeding 98 per cent, with a median velocity accuracy of 20 km s−1 (at z = 0.2). Using the catalogue of 2740 X-ray galaxy clusters confirmed with DR16 spectroscopy, we reveal the 3D map of the galaxy cluster distribution in the observable Universe up to z ∼ 0.6. We highlight the homogeneity of the member galaxy spectra among distinct regions of the galaxy cluster phase space. Aided by accurate spectroscopic redshifts and by a model of the sample selection effects, we compute the galaxy cluster X-ray luminosity function and we present its lack of evolution up to z = 0.6. Finally we discuss the prospects of forthcoming large multiplexed spectroscopic programmes dedicated to follow up the next generation of all-sky X-ray source catalogues.

Clerc, N.↗
DOE OSTI2023

A striking relationship between dust extinction and radio detection in DESI QSOs: evidence for a dusty blow-out phase in red QSOs

ABSTRACT We present the first eight months of data from our secondary target programme within the ongoing Dark Energy Spectroscopic Instrument (DESI) survey. Our programme uses a mid-infrared and optical colour selection to preferentially target dust-reddened quasi-stellar objects (QSOs) that would have otherwise been missed by the nominal DESI QSO selection. So far, we have obtained optical spectra for 3038 candidates, of which ∼70 per cent of the high-quality objects (those with robust redshifts) are visually confirmed to be Type 1 QSOs, consistent with the expected fraction from the main DESI QSO survey. By fitting a dust-reddened blue QSO composite to the QSO spectra, we find they are well-fitted by a normal QSO with up to AV ∼ 4 mag of line-of-sight dust extinction. Utilizing radio data from the LOFAR Two-metre Sky Survey (LoTSS) DR2, we identify a striking positive relationship between the amount of line-of-sight dust extinction towards a QSO and the radio detection fraction, that is not driven by radio-loud systems, redshift and/or luminosity effects. This demonstrates an intrinsic connection between dust reddening and the production of radio emission in QSOs, whereby the radio emission is most likely due to low-powered jets or winds/outflows causing shocks in a dusty environment. On the basis of this evidence, we suggest that red QSOs may represent a transitional ‘blow-out’ phase in the evolution of QSOs, where winds and outflows evacuate the dust and gas to reveal an unobscured blue QSO.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2022

CRISPR-RNAa: targeted activation of translation using dCas13 fusions to translation initiation factors

Abstract Tools for synthetically controlling gene expression are a cornerstone of genetic engineering. CRISPRi and CRISPRa technologies have been applied extensively for programmable modulation of gene transcription, but there are few such tools for targeted modulation of protein translation rates. Here, we employ CRISPR-Cas13 as a programmable activator of translation. We develop a novel variant of the catalytically-deactivated Cas13d enzyme dCasRx by fusing it to translation initiation factor IF3. We demonstrate dCasRx-IF3’s ability to enhance expression 21.3-fold above dCasRx when both are targeted to the start of the 5′ untranslated region of mRNA encoding red fluorescent protein in Escherichia coli. Activation of translation is location-dependent, and we show dCasRx-IF3 represses translation when targeted to the ribosomal binding site, rather than enhancing it. We provide evidence that dCasRx-IF3 targeting enhances mRNA stability relative to dCasRx, providing mechanistic insights into how this new tool functions to enhance gene expression. We also demonstrate targeted upregulation of native LacZ 2.6-fold, showing dCasRx-IF3’s ability to enhance expression of endogenous genes. dCasRx-IF3 requires no additional host modification to influence gene expression. This work outlines a novel approach, CRISPR-RNAa, for post-transcriptional control of translation to activate gene expression.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
DOE OSTI2015

Techniques for Enabling Highly Efficient Message Passing on Many-Core Architectures

Many-core architecture provides a massively parallel environment with dozens of cores and hundreds of hardware threads. Scientific application programmers are increasingly looking at ways to utilize such large numbers of lightweight cores for various programming models. Efficiently executing these models on massively parallel many-core environments is not easy, however and performance may be degraded in various ways. The first author's doctoral research focuses on exploiting the capabilities of many-core architectures on widely used MPI implementations. While application programmers have studied several approaches to achieve better parallelism and resource sharing, many of those approaches still face communication problems that degrade performance. In the thesis, we investigate the characteristics of MPI on such massively threaded architectures and propose two efficient strategies -- a multi-threaded MPI approach and a process-based asynchronous model -- to optimize MPI communication for modern scientific applications.

Si, Min↗
DOE OSTI2025

JACC.shared: Leveraging HPC Metaprogramming and Performance Portability for Computations That Use Shared Memory GPUs

In this work, we present JACC.shared, a new feature of Julia for ACCelerators (JACC), which is the performanceportable and metaprogramming model of the just-in-time and LLVM-based Julia language. This new feature allows JACC applications to leverage the high-performance computing (HPC) capabilities of high-bandwidth, on-chip GPU memory. Historically, exploiting high-bandwidth, shared-memory GPUs has not been a priority for high-level programming solutions. JACC.shared covers that gap for the first time, thereby providing a highlevel, portable, and easy-to-use solution for programmers to exploit this memory and supporting all current major accelerator architectures. Well-known HPC and AI workloads, such as multi/hyperspectral imaging and AI convolutions, have been used to evaluate JACC.shared on two exascale GPU architectures hosted by some of the most powerful US Department of Energy supercomputers: Perlmutter (NVIDIA A100) and Frontier (AMD MI250X). The performance evaluation reports speedup of up to 3.5× by adding only one line of code to the base codes, thus providing important accelerators in a simple, portable, and transparent way and elevating the programming productivity and performance-portability capabilities for Julia/JACC HPC, AI, and scientific applications.

Valero Lara, Pedro [ORNL] (ORCID:0000000214794310)↗
DOE OSTI2015

Modeling Cooperative Threads to Project GPU Performance for Adaptive Parallelism

Most accelerators, such as graphics processing units (GPUs) and vector processors, are particularly suitable for accelerating massively parallel workloads. On the other hand, conventional workloads are developed for multi-core parallelism, which often scale to only a few dozen OpenMP threads. When hardware threads significantly outnumber the degree of parallelism in the outer loop, programmers are challenged with efficient hardware utilization. A common solution is to further exploit the parallelism hidden deep in the code structure. Such parallelism is less structured: parallel and sequential loops may be imperfectly nested within each other, neigh boring inner loops may exhibit different concurrency patterns (e.g. Reduction vs. Forall), yet have to be parallelized in the same parallel section. Many input-dependent transformations have to be explored. A programmer often employs a larger group of hardware threads to cooperatively walk through a smaller outer loop partition and adaptively exploit any encountered parallelism. This process is time-consuming and error-prone, yet the risk of gaining little or no performance remains high for such workloads. To reduce risk and guide implementation, we propose a technique to model workloads with limited parallelism that can automatically explore and evaluate transformations involving cooperative threads. Eventually, our framework projects the best achievable performance and the most promising transformations without implementing GPU code or using physical hardware. We envision our technique to be integrated into future compilers or optimization frameworks for autotuning.

Meng, Jiayuan↗
DOE OSTI2017

Modeling DNP3 Traffic Characteristics of Field Devices in SCADA Systems of the Smart Grid

In the generation, transmission, and distribution sectors of the smart grid, intelligence of field devices is realized by programmable logic controllers (PLCs). Many smart-grid subsystems are essentially cyber-physical energy systems (CPES): For instance, the power system process (i.e., the physical part) within a substation is monitored and controlled by a SCADA network with hosts running miscellaneous applications (i.e., the cyber part). To study the interactions between the cyber and physical components of a CPES, several co-simulation platforms have been proposed. However, the network simulators/emulators of these platforms do not include a detailed traffic model that takes into account the impacts of the execution model of PLCs on traffic characteristics. As a result, network traces generated by co-simulation only reveal the impacts of the physical process on the contents of the traffic generated by SCADA hosts, whereas the distinction between PLCs and computing nodes (e.g., a hardened computer running a process visualization application) has been overlooked. To generate realistic network traces using co-simulation for the design and evaluation of applications relying on accurate traffic profiles, it is necessary to establish a traffic model for PLCs. In this work, we propose a parameterized model for PLCs that can be incorporated into existing co-simulation platforms. We focus on the DNP3 subsystem of slave PLCs, which automates the processing of packets from the DNP3 master. To validate our approach, we extract model parameters from both the configuration and network traces of real PLCs. Simulated network traces are generated and compared against those from PLCs. Our evaluation shows that our proposed model captures the essential traffic characteristics of DNP3 slave PLCs, which can be used to extend existing co-simulation platforms and gain further insights into the behaviors of CPES.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2023

VISILIENCE: An Interactive Visualization Framework for Resilience Analysis using Control-Flow Graph

Soft errors have become one of the major concerns for the error resilience of HPC applications, as those errors can cause HPC applications to generate serious outcomes such as Silent Data Corruptions (SDCs). A large body of approaches has been proposed to analyze the resilience of HPC applications. However, existing studies rarely address the challenges of the analysis result perception. Specifically, resilience analysis techniques often produce a massive volume of unstructured data, making it difficult for programmers to conduct the resilience analysis due to non-intuitive raw data. Furthermore, different analysis models produce diverse results with multiple levels of details, which may create hurdles to compare and explore the resilience of HPC program execution. To this end, we present VISILIENCE, an interactive VISual resILIENCE analysis framework to allow programmers to facilitate the resilience analysis of HPC applications. In particular, VISILIENCE leverages an effective visualization approach Control Flow Graph (CFG) to present a function execution. In addition, three widely-used models for resilience analysis (i.e., Y-Branch, IPAS, and TRIDENT) are seamlessly embedded into the framework for resilience analysis and result comparison. Multiple case studies have been conducted to demonstrate the effectiveness of our proposed framework VISILIENCE.

Jiang, Hailong↗
DOE OSTI2020

Digital zero noise extrapolation for quantum error mitigation

Zero-noise extrapolation (ZNE) is an increasingly popular technique for mitigating errors in noisy quantum computations without using additional quantum resources. We review the fundamentals of ZNE and propose several improvements to noise scaling and extrapolation, the two key components in the technique. We introduce unitary folding and parameterized noise scaling. Furthermore, these are digital noise scaling frameworks, i.e. one can apply them using only gate-level access common to most quantum instruction sets. We also study different extrapolation methods, including a new adaptive protocol that uses a statistical inference framework. Benchmarks of our techniques show error reductions of 18X to 24X over non-mitigated circuits and demonstrate ZNE effectiveness at larger qubit numbers than have been tested previously. In addition to presenting new results, this work is a self-contained introduction to the practical use of ZNE by quantum programmers.

quantum computing↗
DOE OSTI2024

JACC: Leveraging HPC Meta-Programming and Performance Portability with the Just-in-Time and LLVM-based Julia Language

We present JACC (Julia for Accelerators), the first high-level, and performance-portable model for the just-in-time and LLVM-based Julia language. JACC provides a unified and lightweight front end across different back ends available in Julia, enabling the same Julia code to run efficiently on many HPC CPU and GPU targets. We evaluated the performance of JACC for common HPC kernels as well as for the most computationally demanding kernels used in applications, HPCCG, a supercomputing benchmark test for sparse domains, and HARVEY, a blood flow simulator to assist in the diagnosis and treatment of patients suffering from vascular diseases. We carried out the performance analysis on the most advanced US DOE supercomputers: Aurora, Frontier, and Perlmutter. Overall, we show that JACC has a negligible overhead versus vendor-specific solutions, reporting GPU speedups with no extra cost to programmability.

Valero-Lara, Pedro↗
DOE OSTI2024

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION↗
DOE OSTI2013

Design of the Trigger Interface and Distribution Board for TJNAF 12 GeV Upgrade

The design of the Trigger Interface and Distribution (TID) board for the 12 GeV Upgrade at Thomas Jefferson National Accelerator Facility (TJNAF) is described. The TID board distributes a low jitter system clock, synchronized trigger, and synchronized multi-purpose SYNC signal. The TID also initiates readout for the data acquisition front-end crate. With the TID boards, a multi-crate system can be setup for large scale nuclear physics experiments. The TID board can be selectively populated as a Trigger Interface (TI) board, or a Trigger Distribution (TD) board for the 12 GeV upgrade experiments. When the TID is populated as a TI, The TID can be located in the VXS crate and distribute the CLOCK/TRIGGER/SYNC (CTS) through the VXS/P0 connector; it can also be located in the standard VME64 crate, and distribute the CTS through the VME/P2 connector or front panel connectors. It initiates the data acquisition for the front-end crate where the TI is positioned in. When the TID is populated as a TD, it fans out the CTS from the trigger supervisor to the front-end crates through optical fibres. The TD board monitors the trigger processing on the TI boards, and sends feedback to the Trigger Supervisor (TS) board for event readout flow control. A Field Programmable Gate Arrays (FPGA) is utilised on the TID board to provide programmability. The TID board was intensively tested on the bench. The TID production version has been released to industry for contract manufacturing.

Gu, Jianhui W.↗
DOE OSTI2021

EMI Mitigation of a &Cacute;uk-Based Power-Electronic System Using Switching-Sequence-Based Control

Switching-sequence-based control (SBC) laws when designed based on topological switching behavior can have positive effects on slow- and fast-scale dynamics of a power-electronic system (PES). The slow-scale control can encompass fast PES state regulation and tracking, based on predefined objective, while fastscale control can address differential-mode (DM) and commonmode (CM) spectral-peak energy associated with PES switching operation. Such control laws may offer enhanced programmability to conventional PES design where bulky electromagnetic interference (EMI) filters have been traditionally used to reduce EMI of switching power converters to meet EMI regulatory standards. An EMI filter is always a less programmable solution since it is usually designed for the worst-case EMI mitigation and usually overkill for a PES operating under reduced load condition. The control scheme outlined in this article offers EMI mitigation across wide operating regions without compromising PES regulation. Moreover, it does so by use of switching sequences that guarantee the reachability of the PES dynamics using an advanced Lyapunov-function-based approach. SBC is a powerful tool to generate control actions for a PES based on multivariate PES state constraints. Hence, contemporary EMI regulatory standards are used as constraints in the SBC formulation to operate the PES under wide operating regime while autonomously mitigating the EMI levels. The work may be of paramount importance for operating the ultra-fast-transition recent wide-bandgap semiconductor devices like GaN–FET and SiC MOSFET under higher power with increasing switching frequencies, which is usually desirable for increased power density and reduced switching losses. Here, a hardware Cuk–PES operated ´ with GaN–FETs is fabricated and is used for case illustration. It is shown by experimental results how SBC mitigate DM and CM EMI noise of the PES while maintaining regulation even for the higher order nonminimum phase PES, while reducing sensor requirements using state observer derived from the switching model of the PES.

42 ENGINEERING↗
DOE OSTI2022

A Prototype High-Voltage Pulsed Power Supply for Control of the ITER Shattered Pellet Injection System Flyer Plate Valve

A high-voltage pulsed power supply (HVPPS) has been designed, prototyped, and tested for driving an eddy current actuated propellant valve for the International Thermonuclear Experimental Reactor (ITER) disruption mitigation system. The high-voltage (HV) dc supply output voltage is software programmable, and the energy storage capacitor bank can be readily reconfigured as 200, 400, 600, and 800 μ F, enabling testing and optimization of both the valve drive and valve systems. Multiple system parameters are monitored before, during, and after each firing of the valve. The system parameters are both displayed and stored for further analysis. Control of the setup, firing sequence, and data collection is automated using a LabVIEW-based control program. The programmability and reconfigurability of this system collectively provide a flexible and robust platform for system refinement and optimization. In this article, a summary of the system will be provided including operational sequences, HV switching and associated triggering methods and circuits, and results measured while firing a solid frozen pellet. Additionally, planned refinement activities toward meeting all requirements for ITER integration will be discussed.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2022

KokkACC: Enhancing Kokkos with OpenACC

Template metaprogramming is gaining popularity as a high-level solution for achieving performance portability on heterogeneous computing resources. Kokkos is a representative approach that offers programmers high-level abstractions for generic programming while most of the device-specific code generation and optimizations are delegated to the compiler through template specializations. For this, Kokkos provides a set of device-specific code specializations in multiple back ends, such as CUDA and HIP. Unlike CUDA or HIP, OpenACC is a high-level and directive-based programming model. This descriptive model allows developers to insert hints (pragmas) into their code that help the compiler to parallelize the code. The compiler is responsible for the transformation of the code, which is completely transparent to the programmer. This paper presents an OpenACC back end for Kokkos: KokkACC. As an alternative to Kokkos’s existing device-specific back ends, KokkACC is a multi-architecture back end providing a high-productivity programming environment enabled by OpenACC’s high-level and descriptive programming model. Moreover, we have observed competitive performance; in some cases, KokkACC is faster (up to 9×) than NVIDIA’s CUDA back end and much faster than OpenMP’s GPU offloading back end. This work also includes implementation details and a detailed performance study conducted with a set of mini-benchmarks (AXPY and DOT product) and three mini-apps (LULESH, miniFE and SNAP, a LAMMPS proxy mini-app).

Valero Lara, Pedro↗
DOE OSTI2020

Implementation of early psychosis services in Latin America: A scoping review

Abstract Aim The evidence of the effectiveness and cost‐effectiveness of early intervention for psychosis (EIP) services has motivated their implementation worldwide. However, complex interventions of such EIP services require local adaptations to successfully match population needs and cultural differences. Latin America is a heterogenous region where EIP services are progressively being adopted. Our aim is to map such initiatives in the region with a focus on implementation outcomes. Methods A scoping review following the Preferred Reporting Items for Systematic review and Meta‐Analysis extension for Scoping Reviews guidelines was conducted. International and regional databases were searched for publications describing EIP programmes in the region. Besides mapping the services, we described implementation outcomes based on the Standards for Reporting Implementation Studies Checklist. Results Ten articles describing seven EIP initiatives from the region were found. Four countries were represented: Argentina, Brazil, Chile and Mexico. The implementation outcomes reporting was heterogenous, although it was possible to ascertain EIP services are feasible and adequate for the region's context. Also, there is some evidence of effectiveness in terms of reducing hospitalizations and improving symptoms. Information about fidelity measures was scarce and there was no information about costs or cost‐effectiveness. Conclusions Only a small proportion of Latin American countries have adopted EIP services. Although these programmes seem to be feasible and effective, data on other implementation outcomes, such as fidelity, cultural appropriateness, cost‐effectiveness and affordability are not available. This might in part explain why this effective approach has not been yet scaled‐up at nationwide levels.

Aceituno, David↗