Fuzzy logic inference processor: A custom VLSI design for system integration
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Watanabe, Hiroyuki↗
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Memory Network For Distributed Data Processors
Universal Memory Network (UMN) is modular, digital data-communication system enabling computers with differing bus architectures to share 32-bit-wide data between locations up to 3 km apart with less than one millisecond of latency. Makes it possible to design sophisticated real-time and near-real-time data-processing systems without data-transfer "bottlenecks". This enterprise network permits transmission of volume of data equivalent to an encyclopedia each second. Facilities benefiting from Universal Memory Network include telemetry stations, simulation facilities, power-plants, and large laboratories or any facility sharing very large volumes of data. Main hub of UMN is reflection center including smaller hubs called Shared Memory Interfaces.
Bolen, David↗
Using LANDSAT to provide potato production estimates to Columbia Basin farmers and processors
The estimation of potato yields in the Columbia basin is described. The fundamental objective is to provide CROPIX with working models of potato production. A two-pronged approach was used to yield estimation: (1) using simulation models, and (2) using purely empirical models. The simulation modeling approach used satellite observations to determine certain key dates in the development of the crop for each field identified as potatoes. In particular, these include planting dates, emergence dates, and harvest dates. These critical dates are fed into simulation models of crop growth and development to derive yield forecasts. Purely empirical models were developed to relate yield to some spectrally derived measure of crop development. Two empirical approaches are presented: one relates tuber yield to estimates of cumulative intercepted solar radiation, the other relates tuber yield to the integral under GVI (Global Vegetation Index) curve.
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Network of dedicated processors for finding lowest-cost map path
A method and associated apparatus are disclosed for finding the lowest cost path of several variable paths. The paths are comprised of a plurality of linked cost-incurring areas existing between an origin point and a destination point. The method comprises the steps of connecting a purality of nodes together in the manner of the cost-incurring areas; programming each node to have a cost associated therewith corresponding to one of the cost-incurring areas; injecting a signal into one of the nodes representing the origin point; propagating the signal through the plurality of nodes from inputs to outputs; reducing the signal in magnitude at each node as a function of the respective cost of the node; and, starting at one of the nodes representing the destination point and following a path having the least reduction in magnitude of the signal from node to node back to one of the nodes representing the origin point whereby the lowest cost path from the origin point to the destination point is found.
Eberhardt, Silvio P.↗
Design and scheduling for periodic concurrent error detection and recovery in processor arrays
Periodic application of time-redundant error checking provides the trade-off between error detection latency and performance degradation. The goal is to achieve high error coverage while satisfying performance requirements. We derive the optimal scheduling of checking patterns in order to uniformly distribute the available checking capability and maximize the error coverage. Synchronous buffering designs using data forwarding and dynamic reconfiguration are described. Efficient single-cycle diagnosis is implemented by error pattern analysis and direct-mapped recovery cache. A rollback recovery scheme using start-up control for local recovery is also presented.
Wang, Yi-Min↗
Fault tolerance in onboard processors - Protecting efficient FDM demultiplexers
The application of convolutional codes to protect demultiplexer filter banks is demonstrated analytically for efficient implementations. An overview is given of the parameters for the efficient implementations of filter banks, and real convolutional codes are discussed in terms of DSP operations. Methods for composite filtering and parity generation are outlined, and attention is given to the protection of polyphase filter demultiplexing systems. Real convolutional codes can be applied to protect demultiplexer filter banks by employing two forms of low-rate parity calculation to each filter bank. The parity values are computed either by the output with an FIR parity filter or in parallel with the normal processing by a composite filter. Hardware similarities between the filter bank and the main demultiplexer bank permit efficient redeployment of the processing resources to the main processing function in any configuration.
Redinbo, Robert↗
Using a Cray Y-MP as an array processor for a RISC Workstation
As microprocessors increase in power, the economics of centralized computing has changed dramatically. At the beginning of the 1980's, mainframes and super computers were often considered to be cost-effective machines for scalar computing. Today, microprocessor-based RISC (reduced-instruction-set computer) systems have displaced many uses of mainframes and supercomputers. Supercomputers are still cost competitive when processing jobs that require both large memory size and high memory bandwidth. One such application is array processing. Certain numerical operations are appropriate to use in a Remote Procedure Call (RPC)-based environment. Matrix multiplication is an example of an operation that can have a sufficient number of arithmetic operations to amortize the cost of an RPC call. An experiment which demonstrates that matrix multiplication can be executed remotely on a large system to speed the execution over that experienced on a workstation is described.
Lamaster, Hugh↗
Information Switching Processor (ISP) contention analysis and control
Future satellite communications, as a viable means of communications and an alternative to terrestrial networks, demand flexibility and low end-user cost. On-board switching/processing satellites potentially provide these features, allowing flexible interconnection among multiple spot beams, direct to the user communications services using very small aperture terminals (VSAT's), independent uplink and downlink access/transmission system designs optimized to user's traffic requirements, efficient TDM downlink transmission, and better link performance. A flexible switching system on the satellite in conjunction with low-cost user terminals will likely benefit future satellite network users.
Shyy, D.↗
Processor architecture and data buffering
A set of architectures from three major architecture families: stack, register, and memory-to-memory is discussed. It is shown that scalable architectures are not applicable for low-density technologies because they require at least 32 words of local memory. Software support is shown to be capable of bridging the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local memory allocated interprocedurally outperforms scalable architectures with equal sizes local memories and even some with larger size local memories. The performance advantage of unscalable architectures becomes significant when in addition to quality compile-time support, a small cache is added to an unscalable architecture. A 32-register architecture with 512 byte cache executes 20 percent less cycles when compared with an 8-set multiple overlapping set organization.
Mulder, Hans↗
System architecture for asynchronous multi-processor robotic control system
The architecture for the Modular Telerobot Task Execution System (MOTES) as implemented in the Supervisory Telerobotics (STELER) Laboratory is described. MOTES is the software component of the remote site of a local-remote telerobotic system which is being developed for NASA for space applications, in particular Space Station Freedom applications. The system is being developed to provide control and supervised autonomous control to support both space based operation and ground-remote control with time delay. The local-remote architecture places task planning responsibilities at the local site and task execution responsibilities at the remote site. This separation allows the remote site to be designed to optimize task execution capability within a limited computational environment such as is expected in flight systems. The local site task planning system could be placed on the ground where few computational limitations are expected. MOTES is written in the Ada programming language for a multiprocessor environment.
Steele, Robert D.↗
Alaska SAR processor implementation of E-ERS-1
The synthetic aperture radar (SAR) data processing algorithm used by the Alaska SAR Facility (ASF) for the European Space Agency's first Remote-Sensing Satellite (E-ERS-1) SAR data are examined. Preprocessing highlights two features: signal measurement, which includes signal-to-noise ratio, replica measurement, and noise measurement; and Doppler measurement, which includes clutter lock and autofocus. The custom pipeline architecture performs the main processing with controls at the input interface, range correlator, corner-turn memory, azimuth correlator, and multi-look memory. The control software employs a flexible control scheme. The Committee on Earth Observation Satellites (CEOS) format encapsulates the ASF products. System performance for SAR image processing of E-ERS-1 data is reviewed.
Cuddy, David↗
VHSIC processors for remote sensing
A generic data system is briefly described. Its possible application to EOS instrument requirements is considered in the light of a survey of the NASA mission set to be flown over the time span of roughly 1990 to 1995.
Benz, H. F.↗
FORTH direct execution processors in the Hopkins ultraviolet telescope
Engineers at the Johns Hopkins University Applied Physics Laboratory have designed and built two computers which will control and monitor the Hopkins Ultraviolet Telescope, a 1986 Space Shuttle experiment. These computers implement a microcoded FORTH nucleus in a word-addressed AMD 2900 series bit-slice architecture. All programs for them are written in FORTH, which takes the place of assembly language in this architecture.
Ballard, Ben↗
Space data systems: Special purpose flight processors
The technical objectives are to develop high-performance, space-qualifiable, onboard computing, storage, and networking technologies. The topics are presented in viewgraph form and include the following: justification; approach; program description; state-of-the-art assessment; technology challenges; and relationship to external programs.
Henry, Mike↗
Current processor technology survey
This report provides a technology survey on current commercially available microprocessors. This report is part of an effort funded by the Office of Aeronautics, Exploration, and Technology (OAET) and the Space Station Freedom (SSF) Advanced Development program to determine computational needs and capability for advanced automation and robotics. It will be used in conjunction with a user requirements survey to determine a plan to meet computational requirements for future NASA missions.
Liu, Yuan-Kwei↗
A low-cost vector processor boosting compute-intensive image processing operations
Low-cost vector processing (VP) is within reach of everyone seriously engaged in scientific computing. The advent of affordable add-on VP-boards for standard workstations complemented by mathematical/statistical libraries is beginning to impact compute-intensive tasks such as image processing. A case in point in the restoration of distorted images from the Hubble Space Telescope. A low-cost implementation is presented of the standard Tarasko-Richardson-Lucy restoration algorithm on an Intel i860-based VP-board which is seamlessly interfaced to a commercial, interactive image processing system. First experience is reported (including some benchmarks for standalone FFT's) and some conclusions are drawn.
Adorf, Hans-Martin↗
Octave: A MARSYAS post-processor for computer-aideed control system design
MARSYAS is a computer-aided control system analysis package for the simulation and analysis of dynamic systems. In the summer of 1991 MARSYAS was updated to allow for the analysis of sampled-data systems in terms of frequency response, stability, etc. This update was continued during the summer of 1992 in order to extend further MARSYAS commands to the study of sampled data systems. Further work was done to examine the computation of openat transfer functions, root-locii and omega-plane frequency response plots. At the conclusion of the summer of 1992 work, it was proposed that control-system design capability be incorporated into the MARSYAS package. It was decided at that time to develop a separate 'stand-alone' computer-aided control system design (CACSD) package. This report is a brief description of such a package.
Hodel, A. Scottedward↗
The 1992-1993 advanced design program. Part 1: The Mars methane engine project. Part 2: The Mars oxygen processor new furnace
Three constituents of the Martian atmosphere, methane, carbon dioxide, and oxygen, can be used for internal combustion in engines utilized for future space exploration on Mars. These three gases, considered as the test case in this research, will be examined to determine required flow rates needed for combustion and optimization of engine performance. Results of the test case are examined in relation to a base case of methane and air for comparative purposes. Testing of exhaust temperatures, cylinder pressure, and exhaust gas analysis were performed for the base case and test case. Also described is a study utilizing a zirconia cell to convert carbon dioxide into usable oxygen to help support future Mars missions.
Lauer, Stephen↗