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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Scalable Al 2 O 3 –TiO 2 Conductive Oxide Interfaces as Defect Reservoirs for Resistive Switching Devices

Abstract Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here, a simple and scalable material system of conductive oxide interfaces is employed, and their unique properties are leveraged for a new type of resistive switching device. An Al 2 O 3 –TiO 2 ‐based valence‐change resistive switching device, where the conductive oxide interface serves both as the bottom electrode and as a reservoir of defects for switching, is demonstrated. The amorphous–polycrystalline Al 2 O 3 –TiO 2 conductive interface is obtained following the technological path of simplifying the fabrication of the 2D electron gases (2DEGs), making them scalable for practical mass integration. Physical analysis of the device chemistry and microstructure with comprehensive electrical analysis of its switching behavior and performance is combined. The origin of the resistive switching is pinpointed to the conductive oxide interface, which serves both as the bottom electrode and as a reservoir of oxygen vacancies. The latter plays a key role in valence‐change resistive switching devices. The new device, based on scalable and complementary metal–oxide–semiconductor (CMOS)‐technology‐compatible fabrication processes, opens new design spaces toward increased tunability and simplification of the device selection challenge.

36 MATERIALS SCIENCE↗
NASA NTRS1984

Operating systems

A counter operating system creates a hierarchy of levels of abstraction, so that at a given level all details concerning lower levels can be ignored. This hierarchical structure separates functions according to their complexity, characteristic time scale, and level of abstraction. The lowest levels include the system's hardware; concepts associated explicitly with the coordination of multiple tasks appear at intermediate levels, which conduct 'primitive processes'. Software semaphore is the mechanism controlling primitive processes that must be synchronized. At higher levels lie, in rising order, the access to the secondary storage devices of a particular machine, a 'virtual memory' scheme for managing the main and secondary memories, communication between processes by way of a mechanism called a 'pipe', access to external input and output devices, and a hierarchy of directories cataloguing the hardware and software objects to which access must be controlled.

Denning, P. J.↗
DOE OSTI2025

SULI Deliverables Using: Python-B1500 [Slides]

A new electrical setup for testing ECRAM devices is described in this presentation. This presentation details the background of ECRAM devices, how the B1500 is used to program ECRAM devices, and the python GUI that was created for controlling the B1500. ECRAM devices are a form of non-volatile memory. The stored data is the resistance between two of the terminals on the device. Using only the B1500, the ECRAM devices can be programmed and the state read out. This creates a simple, logical testing setup. The overall setup was successful, ECRAM devices could easily be programmed and measured. However, there is still room for improvement. Specifically, in the creation of an automated “Program” feature and a “Data Collection” feature. These features will require additional advances in the understanding of ECRAM devices but will greatly automate and improve the current data collection and application of ECRAM devices.

42 ENGINEERING↗
DOE OSTI2011

Quantum computers: Definition and implementations

The DiVincenzo criteria for implementing a quantum computer have been seminal in focusing both experimental and theoretical research in quantum-information processing. These criteria were formulated specifically for the circuit model of quantum computing. However, several new models for quantum computing (paradigms) have been proposed that do not seem to fit the criteria well. Therefore, the question is what are the general criteria for implementing quantum computers. To this end, a formal operational definition of a quantum computer is introduced. It is then shown that, according to this definition, a device is a quantum computer if it obeys the following criteria: Any quantum computer must consist of a quantum memory, with an additional structure that (1) facilitates a controlled quantum evolution of the quantum memory; (2) includes a method for information theoretic cooling of the memory; and (3) provides a readout mechanism for subsets of the quantum memory. The criteria are met when the device is scalable and operates fault tolerantly. We discuss various existing quantum computing paradigms and how they fit within this framework. Finally, we present a decision tree for selecting an avenue toward building a quantum computer. This is intended to help experimentalists determine the most natural paradigm given a particular physical implementation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2015

Quasi-unipolar pentacene films embedded with fullerene for non-volatile organic transistor memories

Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while the electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Understanding the Impact of Memory Access Patterns in Intel Processors

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

Alaul haque monil, Mohammad↗
NASA NTRS2011

AC Electric Field Activated Shape Memory Polymer Composite

Shape memory materials have drawn interest for applications like intelligent medical devices, deployable space structures and morphing structures. Compared to other shape memory materials like shape memory alloys (SMAs) or shape memory ceramics (SMCs), shape memory polymers (SMPs) have high elastic deformation that is amenable to tailored of mechanical properties, have lower density, and are easily processed. However, SMPs have low recovery stress and long response times. A new shape memory thermosetting polymer nanocomposite (LaRC-SMPC) was synthesized with conductive fillers to enhance its thermo-mechanical characteristics. A new composition of shape memory thermosetting polymer nanocomposite (LaRC-SMPC) was synthesized with conductive functionalized graphene sheets (FGS) to enhance its thermo-mechanical characteristics. The elastic modulus of LaRC-SMPC is approximately 2.7 GPa at room temperature and 4.3 MPa above its glass transition temperature. Conductive FGSs-doped LaRC-SMPC exhibited higher conductivity compared to pristine LaRC SMP. Applying an electric field at between 0.1 Hz and 1 kHz induced faster heating to activate the LaRC-SMPC s shape memory effect relative to applying DC electric field or AC electric field at frequencies exceeding1 kHz.

Kang, Jin Ho↗
NASA NTRSDate not supplied

Design and Analysis of Shape Memory Spring Tires for Martian and Lunar Rover Vehicles

Shape memory alloys (SMAs) have played an important role in various innovative engineering and medical applications, such as aerospace actuators, vibration damping devices, and coronary stents. In applications, shape memory alloys are commonly utilized in two fundamentally different ways: (i) making use of the superelasticity/ pseudoelasticity (SE/PE) phenomena, as in applications in biomedical engineering, and (ii) taking advantages of the shape memory effect (SME), as is used for actuators. Their ability to act in such vastly different capacities is mainly due to their unique capability to recover large amounts of deformation produced by either applied stresses or temperature changes. One recent emerging application in use of SMAs has been in the area of non-pneumatic tire designs for Martian or Lunar roving vehicles. These vehicles require tires that are capable of traversing rugged terrain while withstanding extreme temperatures and atmospheric conditions. Inspired by the flexible wire mesh tires used on three Lunar Roving Vehicle (LRV) missions to the Moon on Apollo 15, 16, and 17, a new compliant tire technology was developed by the NASA Glenn Research Center (GRC) and Goodyear Tire & Rubber, known as the Spring Tire. The Spring Tire consists of several hundred coiled springs woven into a flexible mesh and formed into the shape of a tire. Like the LRV wire mesh tires, the original Spring Tires were made from spring steel and were prone to permanent deformation when undergoing high localized loads. Later, a new iteration of this technology was invented, known as the ‘Superelastic Tire’. This new technology incorporated the use of superelastic SMA springs, which could effectively undergo approximately 30 times more reversible deformation than the steel spring. It also provided even greater durability and allowed for more flexibility in design, such as the use of other structural forms to reduce mass or increase load carrying capacity. Because of the unique nature of both the SMA material and the complex interactions between the springs, designing Spring Tires for a specific application requires extensive effort. Historically, design decisions have relied on full-scale empirical testing; however, this is very expensive and time consuming, especially when multiple iterations are needed. Therefore, developing a large-scale, robust, and predictive numerical model entailing complex spring interactions and the shape memory material behavior within a tire construct is the first essential step towards a successful design program. The current work focuses on implementation of the user-defined Shape Memory Alloy (SMA) model, otherwise known as SMA-GVIPs, in the Finite Element analysis (FEA) program ABAQUS for large-scale simulations of the GRC-developed Spring Tires made of SMA. The novelty of this work lies in the thorough, detail-oriented, and computationally efficient finite element analysis of full-scale SMA tires. A well-thought material characterization plan followed by model validation and a systemic sensitivity study on SMA tires has never been reported in the previous literature. The main objective of this study is to help the team improve and optimize the structural design of the SMA tires through in-depth numerical analysis and sensitivity studies. Various design variables (wire diameter, coil diameter, pitch, bead angle, and number of springs) were varied to study their influence on the global load-displacement response of the tire construct. A detailed investigation of the three-dimensional stress states was also carried out to enhance our understanding of the local changes as the tire goes through global deformation. It was concluded that a robust numerical model with a good predictive capability, together with a thoughtfully crafted sensitivity study can result in improved design iterations required to reach a desired tire performance while, significantly reducing manufacturing, labor and testing expenses. A summary of the Finite Element (FE) model construction will be presented together with a description of the user-defined SMA model, characterization process, experimental results, model validation, and numerical sensitivity study results.

shape memory alloys↗
DOE OSTI2016

Radiation Hardened Electronics Destined For Severe Nuclear Reactor Environments

Post nuclear accident conditions represent a harsh environment for electronics. The full station blackout experience at Fukushima shows the necessity for emergency sensing capabilities in a radiation-enhanced environment. This NEET (Nuclear Energy Enabling Technologies) research project developed radiation hardened by design (RHBD) electronics using commercially available technology that employs commercial off-the-shelf (COTS) devices and present generation circuit fabrication techniques to improve the total ionizing dose (TID) hardness of electronics. Such technology not only has applicability to severe accident conditions but also to facilities throughout the nuclear fuel cycle in which radiation tolerance is required. For example, with TID tolerance to megarads of dose, electronics could be deployed for long-term monitoring, inspection and decontamination missions. The present work has taken a two-pronged approach, specifically, development of both board and application-specific integrated circuit (ASIC) level RHBD techniques. The former path has focused on TID testing of representative microcontroller ICs with embedded flash (eFlash) memory, as well as standalone flash devices that utilize the same fabrication technologies. The standalone flash devices are less complicated, allowing better understanding of the TID response of the crucial circuits. Our TID experiments utilize biased components that are in-situ tested, and in full operation during irradiation. A potential pitfall in the qualification of memory circuits is the lack of rigorous testing of the possible memory states. For this reason, we employ test patterns that include all ones, all zeros, a checkerboard of zeros and ones, an inverse checkerboard, and random data. With experimental evidence of improved radiation response for unbiased versus biased conditions, a demonstration-level board using the COTS devices was constructed. Through a combination of redundancy and power gating, the demonstration board exhibits radiation resilience to over 200 krad. Furthermore, our ASIC microprocessor using RHBD techniques was shown to be fully functional after an exposure of 2.5 Mrad whereas the COTS microcontroller units failed catastrophically at <100 krad. The methods developed in this work can facilitate the long-term viability of radiation-hard robotic systems, thereby avoiding obsolescence issues. As a case in point, the nuclear industry with its low purchasing power does not drive the semiconductor industry strategic plans, and the rapid advancements in electronics technology can leave legacy systems stranded.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2016

Correlated memory resistor in epitaxial NdNiO{sub 3} heterostructures with asymmetrical proton concentration

The electronic devices using correlated transition metal oxides are the promising candidates to overcome the limitation of the current electronics due to the rich electronic phases and the extreme sensitivities. Here, we report proton-based resistive switching memory that uses correlated oxides, i.e., epitaxial NdNiO{sub 3} heterostructure with asymmetrical concentration of protons (H{sup +}) to obtain multilevel states. By designing such metal-NdNiO{sub 3}-metal device structures with asymmetrical proton concentration, we demonstrate that the correlated oxides exhibit resistive switching by ionic transport of protons at the metal-hydrogenated NdNiO{sub 3} (H-NNO) interface. This finding will guide the development of energy-efficient switching devices for non-volatile memory and neuromorphic applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. Further, the different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

36 MATERIALS SCIENCE↗
NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗
DOE OSTI2015

GraphReduce: Processing Large-Scale Graphs on Accelerator-Based Systems

Recent work on real-world graph analytics has sought to leverage the massive amount of parallelism offered by GPU devices, but challenges remain due to the inherent irregularity of graph algorithms and limitations in GPU-resident memory for storing large graphs. We present GraphReduce, a highly efficient and scalable GPU-based framework that operates on graphs that exceed the device’s internal memory capacity. GraphReduce adopts a combination of edge- and vertex-centric implementations of the Gather-Apply-Scatter programming model and operates on multiple asynchronous GPU streams to fully exploit the high degrees of parallelism in GPUs with efficient graph data movement between the host and device.

Architecture optimization, reuse, performance, ene↗
DOE OSTI2015

GraphReduce: Large-Scale Graph Analytics on Accelerator-Based HPC Systems

Recent work on real-world graph analytics has sought to leverage the massive amount of parallelism offered by GPU devices, but challenges remain due to the inherent irregularity of graph algorithms and limitations in GPU-resident memory for storing large graphs. We present GraphReduce, a highly efficient and scalable GPU-based framework that operates on graphs that exceed the device’s internal memory capacity. GraphReduce adopts a combination of both edge- and vertex-centric implementations of the Gather-Apply-Scatter programming model and operates on multiple asynchronous GPU streams to fully exploit the high degrees of parallelism in GPUs with efficient graph data movement between the host and the device.

Architecture optimization, reuse, performance, ene↗
NASA NTRS2011

Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

John, Caroline S.↗
NASA NTRS1992

Development of A Non-Explosive Release Device for Aerospace Applications

A simple, non-explosive, high load-capacity release mechanism using shape memory alloy is currently being developed for space flight. This device, the Frangibolt, could replace most pyrotechnic devices in applications where the need for safety, reliability, non-destructive testing, and minimal mechanical shock is more crucial than the need for rapid actuation. Prototype hardware has been designed, tested, and proven in laboratory conditions. Operation and demonstration of these devices evidenced reliable and repeatable performance, clearly indicating that extensive testing for flight qualification is warranted. Here, the Frangibolt design is discussed, recent test results of laboratory units are described, and the work that must be performed in the upcoming months to qualify the device for aerospace applications is addressed.

John D Busch↗
DOE OSTI2023

Towards generic memory forensic framework for programmable logic controllers

A Programmable Logic Controller (PLC) is a microprocessor-based controller that is used to automate physical processes in critical infrastructure and various other industries and manufacturing sectors. Initially, PLCs were completely isolated from the Internet, and cyber security was not incorporated at the time of development. The introduction of industry 4.0 and the evolution of ICS systems to communicate over public IP addresses from the Internet enhanced productivity and efficiency, but Internet connectivity exposed the systems and their vulnerabilities, which led to an increase in cyber attacks. When a system is sabotaged/compromised, security analysts need to get to the root cause of the attack as quickly as possible to recover the system. To do so, memory forensic analysis is critical to provide a unique insight into the run-time memory activities and extract a reliable source of evidence. In this paper, we analyze the memory structure of the Schneider Electric Modicon M221 PLC. To build a memory profile, we reverse engineer the communication protocol and conduct differential analysis to gain knowledge about the structure of the memory and the low-level representation of control logic instructions. We then identify dynamic and static memory regions by modifying different project fields and conducting differential analysis, which allows us to identify boundaries of critical memory structures and extract important forensic artifacts that can be found in the memory. The Python implementation of the memory profile can help reduce the time and effort required for manual analysis in case of cyber incident or system failure.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Data movement engine

A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. A description of the rearranged data is maintained in a metadata memory region. Rearranged data may be accessed by one or more host processing units. Write-back of data from the destination to the source region may be reduced by use of Bloom filter or the like.

Beard, Jonathan Curtis↗