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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Circuit increases the range of a logarithmic current amplifier by combining a commercially available amplifier with a silicon epitaxial transistor. A temperature compensating network is provided for the transistor.
Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.
Slide rule enables the ready conversion of transistor h parameters from one form to another and reduces calculation time by a factor of 5 to 10. The scales are selected to cover all ranges of each parameter that will normally exist for any transistor, and answers are given in the correct order of magnitude, making powers-of-ten calculations unnecessary.
Quantative relationships between radiation dosage to transistors and resultant damage are established. Calculation of these dose levels is based on high energy particle population data and analysis of the shielding effect provided by the enclosures surrounding a given transistor.
Base-triggered avalanche transistor circuit used in a Marx bank pulser configuration provides voltage multiplication with nanosecond rise-time. The avalanche-mode transistors replace conventional spark gaps in the Marx bank. The delay time from an input signal to the output signal to the output is typically 6 nanoseconds.
Extrapolation tables for the control of silicon transistor product reliability have been compiled. The tables are based on a version of the Arrhenius statistical relation and are intended to be used for low- and medium-power silicon transistors.
Modification of process for fabricating transistors, which comprises a metallization-pattern design for emitter and base areas together with a double bonding configuration for each emitter and base-bonding lead, improves uniformity of carrier injection in transistors and of reducing lead inductances at base-emitter terminals.
Bipolar n-p-n transistors fabrication to increase driving capabilities of complementary MOS transistors while retaining low power dissipation
GaAs-Ge heterojunction transistors with microwave planar geometry, calculating performance for comparison with Ge homojunction transistor
Reactor inserted in the base-drive circuit of each power transistor delays the turn-on of one transistor until the other has turned off.
Techniques were developed for creating bipolar microwave transistors in GaAs by ion implantation doping. The electrical properties of doped layers produced by the implantation of the light ions Be, Mg, and S were studied. Be, Mg, and S are suitable for forming the relatively deep base-collector junction at low ion energies. The electrical characteristics of ion-implanted diodes of both the mesa and planar types were determined. Some n-p-n planar transistor structures were fabricated by implantation of Mg to form the base regions and Si to form the emitters. These devices were found to have reasonably good base-collector and emitter-base junctions, but the current gain beta was small. The low was attributable to radiative recombination in the base region, which was extremely wide.
Assembly of two individually encapsulated silicon-chip transistors produces silicon power-transistor that has low electrical resistance and low thermal impedance. Electrical resistance and thermal impedance are low because of short lead lengths, and external contact surfaces are plated to reduce resistance at interfaces.
This program was to develop a ruggedized transistor capable of meeting the following CW objectives at 2.3 gigahertz: a power output of 20 watts, a power gain of 6 db, and an efficiency of 40 percent. Devices developed produced the following CW performance at 2.3 gigahertz: a power output of 23 watts, a power gain of 7.7 db, and an efficiently of 40.0 percent. This performance was achieved with an eight-cell TA8407 transistor design having the following modifications: a thin pellet, high-frequency diffusion, high-level emitter ballasting, an optimized emitter-bonding configuration for uniform power sharing, and a package that provides for some internal matching through the use of distributed line techniques.
It is shown that an economically justified choice of regime and conditioning time for transistors for equipment of increased reliability is impossible without analyzing the stabilization time of the transistor parameters. The optimal regime and conditioning time are well founded. A method is presented for evaluating the optimal conditioning time by technical economic indexes.
A family of five static dc-to-square-wave inverters, each employing a square-loop magnetic core in conjunction with two switching transistors, is analyzed using piecewise-linear models for the nonlinear characteristics of the transistors, diodes, and saturable-core devices. Four of the inverters are analyzed in detail for the first time. These analyses show that, by proper choice of a frame of reference, each of the five quite differently appearing inverter circuits can be described by a common equivalent circuit. This equivalent circuit consists of a five-segment nonlinear resistor, a nonlinear saturable reactor, and a linear capacitor. Thus, by proper interpretation and identification of the parameters in the different circuits, the results of a detailed solution for one of the inverter circuits provide similar information and insight into the local and global behavior of each inverter in the family.
A pulse charger which uses water-cooled 1000-amp transistor switches has been developed to determine empirically the best methods of rapidly charging large cells in the one- to two-volt range. The pulse charger is capable of delivering a positive current from 0 to 1000 amps and extracting a negative current from 0 to 1000 amps. The charger can supply a 1000-amp DC charge or can switch 1000 amps at a rate of 1000 Hz. Special attention is given to problems associated with rapid switching of high currents through use of transistors.
TO63 transistor package can operate in hydraulic oil ar pressures of 200 psi or greater without leakage failure if it is reinforced by alumina disk brazed to cap and terminals. This inexpensive modification has been used successfully on power transistors in hydraulic circulating-pump assemblies for Space Shuttle orbiter and should be effective in other pressurized environments, such as in oil exploration equipment.
CADAT field-effect transistor simulator (FETSIM) analyzes dc and transient behavior of metal-oxide-semiconductor (MOS) circuits. Both N-MOS and P-MOS transistor configurations in either bulk of silicon-on-sapphire (SOS) technology and almost any combination of R/C elements are analyzed.