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At least 109 records · Page 6

Solder Joint Health Monitoring Testbed

A method of monitoring the health of selected solder joints, called SJ-BIST, has been developed by Ridgetop Group Inc. under a Small Business Innovative Research (SBIR) contract. The primary goal of this research program is to test and validate this method in a flight environment using realistically seeded faults in selected solder joints. An additional objective is to gather environmental data for future development of physics-based and data-driven prognostics algorithms. A test board is being designed using a Xilinx FPGA. These boards will be tested both in flight and on the ground using a shaker table and an altitude chamber.

Delaney, Michael M.

Soldering in a Reduced Gravity Environment (SoRGE)

Future long-duration human exploration missions will be challenged by constraints on mass and volume allocations available for spare parts. Addressing this challenge will be critical to the success of these missions. As a result, it is necessary to consider new approaches to spacecraft maintenance and repair that reduce the need for large replacement components. Currently, crew members on the International Space Station (ISS) recover from faults by removing and replacing, using backup systems, or living without the function of Orbital Replacement Units (ORUs). These ORUs are returned to a depot where the root cause of the failure is determined and the ORU is repaired. The crew has some limited repair capability with the Modulation/DeModulation (MDM) ORU, where circuit cards are removed and replace in faulty units. The next step to reducing the size of the items being replaced would be to implement component-level repair. This mode of repair has been implemented by the U.S. Navy in an operational environment and is now part of their standard approach for maintenance. It is appropriate to consider whether this approach can be adapted for future spaceflight operations. To this end, the Soldering in a Reduced Gravity Environment (SoRGE) experiment studied the effect of gravity on the formation of solder joints on electronic circuit boards. This document describes the SoRGE experiment, the analysis methods, and results to date. This document will also contain comments from the crew regarding their experience conducting the SoRGE experiment as well as recommendations for future improvements. Finally, this document will discuss the plans for the SoRGE samples which remain on ISS.

Easton, John W.

On-PIC Light Source Integration & Micro-dispensing of Solder Paste for Flip Chip Application

To reach the next level benefits of photonic integrated circuits (PICs), the Integrated Photonic Systems Roadmap-International describes the necessity of either heterogeneous or hybrid integration of light sources [1]. A new approach for hybrid integration is Photonic Wire Bonding where 3D nanolithography is used to pattern a polymer waveguide that connects light sources to PIC waveguides. The waveguides resemble electrical wire bonds and essentially do the same as their electrical counterpart for packaging photonic chips together. In order to reap the full benefits of a photonic wire bonds, the light source must be carefully packaged. In this work I seek to expand RIT’s photonic packaging capability by establishing a packaging process to integrate light sources, specifically an Indium Phosphide distributed feedback lasers and a reflective semiconductor optical amplifiers, directly onto a photonic integrated circuits. Another necessary requirement for PIC packaging is densely integrated electrical connectivity. In this thesis I developed a fine pitch flip chip interconnect technique demonstrated using gold stud bumps in conjunction with micro-dispensed solder paste. This work opens the door to high density photonic flip chip applications. The micro-dispensed solder paste dots having diameters 50-125 µm are currently being tested at a pitch of 150 µm . The gold stud bumps are formed with 1mil gold wire creating bumps with a diameter of 40-60 µm depending on specific parameter values. These capabilities will allow RIT to assemble and test novel photonic integrated devices, cutting down on the time and cost associated with third party assembly and tests facilities. Thereby keeping RIT at the forefront of photonic research.

Wongk, Nicole

(abstract) A Brief, Selective Review of Thermal Cycling Fatigue in Eutectic Tin-Lead Solder

This paper reviews selected parts of the current literature relevant to thermo-mechanical fatigue mechanisms in eutectic tin-lead solder, and suggests a general outline to account for some observed failures. The field is found to be complex. One recent experimental study finds some failure modes to be sensitive to joint geometry. Attempts to extrapolate from test environments to service environments have had only limited success. Much work remains to be done before fatigue failures in this material can be considered as under practical control.

environments

Solder joint fatigue analysis under low temperature Martian conditions

Electronics, without requiring heater power or enclosure in a centralized 'warm electronics box,' will need to survive mean surface temperatures of -120 degrees Celsius to +20 degrees Celsius for an extended Martian mission and an operational temperature up to 85 degrees Celsisus. Since these electronics will need to survive extended cycles under these conditions, fatigue is a significant concern. The solder joint reliability of connectors on a printed wiring board was investigated.

low temperature

Fixture aids soldering of electronic components on circuit board

Spring clamp fixture holds small electronic components in a desired position while they are being soldered on a circuit board. The spring clamp is clipped on the edge of the circuit board and an adjustable spring-steel boom holds components against the board. The felt pad at the end of the boom is replaced with different attachments for other holding tasks.

Ross, M. H.