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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2016

Rendering and Compositing Infrastructure Improvements to VisIt for Insitu Rendering

Compared to posthoc rendering, insitu rendering often generates larger numbers of images, as a result rendering performance and scalability are critical in the insitu setting. In this work we present improvements to VisIt's rendering and compositing infrastructure that deliver increased performance and scalability in both posthoc and insitu settings. We added the capability for alpha blend compositing and use it with ordered compositing when datasets have disjoint block domain decomposition to optimize the rendering of transparent geometry. We also made improvements that increase overall efficiency by reducing communication and data movement and have addressed a number of performance issues. We structured our code to take advantage of SIMD parallelization and use threads to overlap communication and compositing. We tested our improvements on a 20 core workstation using 8 cores to render geometry generated from a $256^3$ cosmology dataset and on a Cray XC31 using 512 cores to render geometry generated from a $2000^2 \times 800$ plasma dataset. Our results show that ordered compositing provides a speed up of up to $4 \times$ over the current sort first strategy. The other improvements resulted in modest speed up with one notable exception where we achieve up to $40 \times$ speed up of rendering and compositing of opaque geometry when both opaque and transparent geometry are rendered together. We also investigated the use of depth peeling, but found that the implementation provided by VTK is substantially slower,both with and without GPU acceleration, than a local camera order sort.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

The Institute for Sustained Performance, Energy, and Resilience Final Project Report

Over the course of the five years of the Scientific Discovery through Advanced Computation (SciDAC-3) program, computational scientists working on behalf of the Department of Energy's Office of Science (DOE SC) exploited a new generation of petascale computing resources to make previously inaccessible discoveries in a broad range of disciplines including physics, chemistry, and materials science. The computing systems underpinning this work increased in performance potential from tens to hundreds of PFlop/s, but in the process evolving significantly from architectures in 2011, when SciDAC-3 began. Although Moore's law continues unabated, the end of Dennard scaling has necessitated a fundamental shift in computer architecture focused on power efficiency. To that end, processors are increasingly varied as they strive to satisfy performance, productivity, reliability, and energy efficiency in the face of divergent computational requirements. The diversity among these machines presents a number of challenges to merely porting today's scientific applications, much less achieving good performance. Therefore, at the beginning of SciDAC-3, USC and its collaborators anticipated that both vastly increased scale (e.g., more chips, more cores per chip, wider SIMD) and heterogeneity would exacerbate performance optimization challenges while simultaneously promoting the issues of energy and heterogeneity will exacerbate performance optimization challenges while simultaneously promoting the issues of energy consumption and resilience to the forefront. To ensure that DOE's computational scientists could successfully exploit emerging high performance computing (HPC) systems, DOE SC’s Advanced Scientific Computing Research Program (ASCR) funded the SciDAC-3 Institute for Sustained Performance, Energy, and Resilience (SUPER). Led by USC, this was a broadly based project with expertise in compilers and system tools, performance engineering, energy management, and resilience. SUPER followed the successful model developed in the previous SciDAC-2 Performance Engineering Research Institute (PERI) of leveraging the research investments DOE and others have made and integrating the results to create new capabilities beyond the reach of any one group. To accomplish this, SUPER was organized into multi-institution teams conducting the research activities in performance portability, energy efficiency, exascale resilience, and overall optimization. SUPER researchers also collaborated with other SciDAC-3 institutes, 13 of the 19 Scientific Computation Application Partnerships (SAP), as well as the broader DOE computational sciences community. These collaborations both focused our research on the real challenges facing petascale scientific computing as well as ensured the broad and immediate impact of the results of our research.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Generating Billion-Edge Scale-Free Networks in Seconds: Performance Study of a Novel GPU-based Preferential Attachment Model

A novel parallel algorithm is presented for generating random scale-free networks using the preferential-attachment model. The algorithm, named cuPPA, is custom-designed for single instruction multiple data (SIMD) style of parallel processing supported by modern processors such as graphical processing units (GPUs). To the best of our knowledge, our algorithm is the first to exploit GPUs, and also the fastest implementation available today, to generate scale free networks using the preferential attachment model. A detailed performance study is presented to understand the scalability and runtime characteristics of the cuPPA algorithm. In one of the best cases, when executed on an NVidia GeForce 1080 GPU, cuPPA generates a scale free network of a billion edges in less than 2 seconds.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

PIMS: Memristor-Based Processing-in-Memory-and-Storage.

Continued progress in computing has augmented the quest for higher performance with a new quest for higher energy efficiency. This has led to the re-emergence of Processing-In-Memory (PIM) ar- chitectures that offer higher density and performance with some boost in energy efficiency. Past PIM work either integrated a standard CPU with a conventional DRAM to improve the CPU- memory link, or used a bit-level processor with Single Instruction Multiple Data (SIMD) control, but neither matched the energy consumption of the memory to the computation. We originally proposed to develop a new architecture derived from PIM that more effectively addressed energy efficiency for high performance scientific, data analytics, and neuromorphic applications. We also originally planned to implement a von Neumann architecture with arithmetic/logic units (ALUs) that matched the power consumption of an advanced storage array to maximize energy efficiency. Implementing this architecture in storage was our original idea, since by augmenting storage (in- stead of memory), the system could address both in-memory computation and applications that accessed larger data sets directly from storage, hence Processing-in-Memory-and-Storage (PIMS). However, as our research matured, we discovered several things that changed our original direc- tion, the most important being that a PIM that implements a standard von Neumann-type archi- tecture results in significant energy efficiency improvement, but only about a O(10) performance improvement. In addition to this, the emergence of new memory technologies moved us to propos- ing a non-von Neumann architecture, called Superstrider, implemented not in storage, but in a new DRAM technology called High Bandwidth Memory (HBM). HBM is a stacked DRAM tech- nology that includes a logic layer where an architecture such as Superstrider could potentially be implemented.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

ATDM ASD report for ECP October 2018

In October the team merged in updated ATDM/Trilinos configuration to include SPARC requirements. Assisted and worked on issues identified by the EMPIRE switchover to the ATDM/Trilinos configuration. Progress was made on automating dashboard triaging. Discovered and began addressing issues with mixed language calling with gcc-7.2 on Power8. Worked on new Python tool to filter CDASH reports to only show new issues. Completed ECP ST review. In October the team put an algorithm in place to prevent inverted elements in SPARC during refinement and worked on tests to morph mesher and should be ready for SGM integration soon. The team worked on solver rebalance and corrected issues. Complete SIMD work. Worked out next steps for solver improvements for EMPIRE. Adjusted some solver settings and to improve performance; strong scaling curves are flat instead of ascending etc. Worked on optimizing kernels for SPARC. Completed ECP ST reviews. The team worked on cleaning up branch for merge into SPARC master dev branch. Progress was made building scripts for catalyst builds on all HPC platforms of interest. Worked on adding TuckerMPl reader as plugin for catalyst. Completed ECP project review. Work has continued on NimbleSM, which now runs in a container and can be used modularly with an MPI code. The team also made progress on a qthreads version of NibleSM. Worked on build system issues within NimbleSM and Sierra for GPUs. Progressed on getting kookfied material models in NimbleSM. The team incorporated panel feedback form ECP project reviews into FY19 plans.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

xSDK-batched Subcontract - Ginkgo Batched Iterative Solver Development (Final Report)

Iterative solvers are fundamentally different from direct solvers in terms of execution as they generally do not execute a pre-defined sequence of operations or steps, but adapt the number of iterations to the specific problem and the preset solution quality. Generally, the adaptation of the iteration count to the problem is realized by monitoring the solver convergence and stopping the iteration process once the monitored metric, e.g., the residual norm, hits a pre-defined threshold. When addressing a set of problems with different properties, it is necessary to monitor the threshold for each problem individually and break up the SIMD execution style to avoid excess iterations for “easier” problems. Ginkgo integrates a simple but customizable stopping criterion for the residual norm and generally uses a pre-defined (relative or absolute) residual norm as the stopping criterion. In order to avoid the overhead of launching a kernel at every iteration, the iteration convergence and iteration control is part of the solver kernel. Each thread maintains its own copy of the iteration count.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Summer Internship Report: ARA2 Benchmarking

Over the past decade, the RISC-V Instruction Set Architecture (ISA) has emerged as a significant player in both academic and industrial processor design due to its open-source nature, modular extension system, and versatility across domains ranging from microcontrollers to high-performance computing (HPC). One of its most important recent advancements is the RISC-V Vector Extension (RVV), which enables explicit data-level parallelism through vector registers and vectorized instructions. Unlike traditional SIMD (Single Instruction, Multiple Data) architectures that fix vector lengths at design time, RVV uses the concept of VLEN (vector register length) as a hardware-independent parameter and allows software to adapt dynamically to the available vector width. This flexible approach ensures portability across implementations while enabling scalable performance. The ARA2 core is a parameterizable RISC-V vector processor developed at the Integrated Systems Lab at ETH Zürich and the University of Bologna. Designed as a tightly-coupled accelerator to a scalar RISC-V core, ARA2 implements the RVV 1.0 specification and offers tunable architectural parameters such as the number of vector lanes, VLEN, and cache sizes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Refactoring the elastic–viscous–plastic solver from the sea ice model CICE v6.5.1 for improved performance

This study focuses on the performance of the elastic–viscous–plastic (EVP) dynamical solver within the sea ice model, CICE v6.5.1. The study has been conducted in two steps. First, the standard EVP solver was extracted from CICE for experiments with refactored versions, which are used for performance testing. Second, one refactored version was integrated and tested in the full CICE model to demonstrate that the new algorithms do not significantly impact the physical results. The study reveals two dominant bottlenecks, namely (1) the number of Message Parsing Interface (MPI) and Open Multi-Processing (OpenMP) synchronization points required for halo exchanges during each time step combined with the irregular domain of active sea ice points and (2) the lack of single-instruction, multiple-data (SIMD) code generation. The standard EVP solver has been refactored based on two generic patterns. The first pattern exposes how general finite differences on masked multi-dimensional arrays can be expressed in order to produce significantly better code generation by changing the memory access pattern from random access to direct access. The second pattern takes an alternative approach to handle static grid properties. The measured single-core performance improvement is more than a factor of 5 compared to the standard implementation. The refactored implementation of strong scales on the Intel® Xeon® Scalable Processors series node until the available bandwidth of the node is used. For the Intel® Xeon® CPU Max series, there is sufficient bandwidth to allow the strong scaling to continue for all the cores on the node, resulting in a single-node improvement factor of 35 over the standard implementation. This study also demonstrates improved performance on GPU processors.

58 GEOSCIENCES↗
NASA NTRS1985

MIMD computing in the USA - 1984

It is often said that the 1980s are becoming the decade of multiinstruction stream or MIMD computers, while the 1970s could be described as the decade of the SIMD (single instruction stream multiple data stream) computers. The availability of microprocessors and VLSI facilities has led to the proposal and construction of novel computer architectures based on linking many hundreds or even thousands of microprocessors, or specially designed VLSI chips. Some of the larger manufacturers offer computers with a small number of CPUs. Because of the variety of the new developments, it was decided to conduct a survey of proposed and existing MIMD computers in the U.S., taking into account a simple classification of the different devices. Particular attention is given to computers which are designed for numerical work with floating-point numbers and the solution of large problems in physics, chemistry, and engineering.

Hockney, R. W.↗
NASA NTRS1987

Solving the Cauchy-Riemann equations on parallel computers

Discussed is the implementation of a single algorithm on three parallel-vector computers. The algorithm is a relaxation scheme for the solution of the Cauchy-Riemann equations; a set of coupled first order partial differential equations. The computers were chosen so as to encompass a variety of architectures. They are: the MPP, and SIMD machine with 16K bit serial processors; FLEX/32, an MIMD machine with 20 processors; and CRAY/2, an MIMD machine with four vector processors. The machine architectures are briefly described. The implementation of the algorithm is discussed in relation to these architectures and measures of the performance on each machine are given. Simple performance models are used to describe the performance. These models highlight the bottlenecks and limiting factors for this algorithm on these architectures. Conclusions are presented.

Fatoohi, Raad A.↗
NASA NTRS1987

Particle simulation of plasmas on the massively parallel processor

Particle simulations, in which collective phenomena in plasmas are studied by following the self consistent motions of many discrete particles, involve several highly repetitive sets of calculations that are readily adaptable to SIMD parallel processing. A fully electromagnetic, relativistic plasma simulation for the massively parallel processor is described. The particle motions are followed in 2 1/2 dimensions on a 128 x 128 grid, with periodic boundary conditions. The two dimensional simulation space is mapped directly onto the processor network; a Fast Fourier Transform is used to solve the field equations. Particle data are stored according to an Eulerian scheme, i.e., the information associated with each particle is moved from one local memory to another as the particle moves across the spatial grid. The method is applied to the study of the nonlinear development of the whistler instability in a magnetospheric plasma model, with an anisotropic electron temperature. The wave distribution function is included as a new diagnostic to allow simulation results to be compared with satellite observations.

Gledhill, I. M. A.↗
NASA NTRS1987

Ray tracing on the MPP

Generating graphics to faithfully represent information can be a computationally intensive task. A way of using the Massively Parallel Processor to generate images by ray tracing is presented. This technique uses sort computation, a method of performing generalized routing interspersed with computation on a single-instruction-multiple-data (SIMD) computer.

Dorband, John E.↗
NASA NTRS1987

The factorization of large composite numbers on the MPP

The continued fraction method for factoring large integers (CFRAC) was an ideal algorithm to be implemented on a massively parallel computer such as the Massively Parallel Processor (MPP). After much effort, the first 60 digit number was factored on the MPP using about 6 1/2 hours of array time. Although this result added about 10 digits to the size number that could be factored using CFRAC on a serial machine, it was already badly beaten by the implementation of Davis and Holdridge on the CRAY-1 using the quadratic sieve, an algorithm which is clearly superior to CFRAC for large numbers. An algorithm is illustrated which is ideally suited to the single instruction multiple data (SIMD) massively parallel architecture and some of the modifications which were needed in order to make the parallel implementation effective and efficient are described.

Mckurdy, Kathy J.↗
NASA NTRS1987

Implementation of an ADI method on parallel computers

The implementation of an ADI method for solving the diffusion equation on three parallel/vector computers is discussed. The computers were chosen so as to encompass a variety of architectures. They are: the MPP, an SIMD machine with 16K bit serial processors; FLEX/32, an MIMD machine with 20 processors; and CRAY/2, an MIMD machine with four vector processors. The Gaussian elimination algorithm is used to solve a set of tridiagonal systems on the FLEX/32 and CRAY/2 while the cyclic elimination algorithm is used to solve these systems on the MPP. The implementation of the method is discussed in relation to these architectures and measures of the performance on each machine are given. Simple performance models are used to describe the performance. These models highlight the bottlenecks and limiting factors for this algorithm on these architectures. Finally, conclusions are presented.

Fatoohi, Raad A.↗
NASA NTRS1987

Supercomputing of supersonic flows using upwind relaxation and MacCormack schemes

The performance of two numerical solution schemes, (1) an implicit upwind relaxation with a finite-volume discretization (Thomas and Walters, 1985) and (2) an explicit-implicit MacCormack (1981) scheme with a finite-difference discretization, is compared in two-dimensional simulations of supersonic flow past a flat plate with leading edge, a rearward-facing step, a 10-deg compression corner, a NACA 0012 airfoil at high angle of attack, and a cavity. The algebraic turbulence model, the solution methods, and the boundary conditions and SIMD coding are explained, and the results are presented in tables and graphs and characterized with reference to published experimental data. Scheme (1) is found to converge more rapidly and to give more accurate results than (2) in a wide range of problem types.

Baysal, O.↗
NASA NTRS1987

Implementation of an ADI method on parallel computers

In this paper the implementation of an ADI method for solving the diffusion equation on three parallel/vector computers is discussed. The computers were chosen so as to encompass a variety of architectures. They are the MPP, an SIMD machine with 16-Kbit serial processors; Flex/32, an MIMD machine with 20 processors; and Cray/2, an MIMD machine with four vector processors. The Gaussian elimination algorithm is used to solve a set of tridiagonal systems on the Flex/32 and Cray/2 while the cyclic elimination algorithm is used to solve these systems on the MPP. The implementation of the method is discussed in relation to these architectures and measures of the performance on each machine are given. Simple performance models are used to describe the performance. These models highlight the bottlenecks and limiting factors for this algorithm on these architectures. Finally conclusions are presented.

Fatoohi, Raad A.↗
NASA NTRS1988

A sparse matrix algorithm on the Boolean vector machine

VLSI technology is being used to implement a prototype Boolean Vector Machine (BVM), which is a large network of very small processors with equally small memories that operate in SIMD mode; these use bit-serial arithmetic, and communicate via cube-connected cycles network. The BVM's bit-serial arithmetic and the small memories of individual processors are noted to compromise the system's effectiveness in large numerical problem applications. Attention is presently given to the implementation of a basic matrix-vector iteration algorithm for space matrices of the BVM, in order to generate over 1 billion useful floating-point operations/sec for this iteration algorithm. The algorithm is expressed in a novel language designated 'BVM'.

Wagner, Robert A.↗
NASA NTRS1989

A VLSI chip set for real time vector quantization of image sequences

The architecture and implementation of a VLSI chip set that vector quantizes (VQ) image sequences in real time is described. The chip set forms a programmable Single-Instruction, Multiple-Data (SIMD) machine which can implement various vector quantization encoding structures. Its VQ codebook may contain unlimited number of codevectors, N, having dimension up to K = 64. Under a weighted least squared error criterion, the engine locates at video rates the best code vector in full-searched or large tree searched VQ codebooks. The ability to manipulate tree structured codebooks, coupled with parallelism and pipelining, permits searches in as short as O (log N) cycles. A full codebook search results in O(N) performance, compared to O(KN) for a Single-Instruction, Single-Data (SISD) machine. With this VLSI chip set, an entire video code can be built on a single board that permits realtime experimentation with very large codebooks.

Baker, Richard L.↗