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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1997

Production Support Flight Control Computers: Research Capability for F/A-18 Aircraft at Dryden Flight Research Center

NASA Dryden Flight Research Center (DFRC) is working with the United States Navy to complete ground testing and initiate flight testing of a modified set of F/A-18 flight control computers. The Production Support Flight Control Computers (PSFCC) can give any fleet F/A-18 airplane an in-flight, pilot-selectable research control law capability. NASA DFRC can efficiently flight test the PSFCC for the following four reasons: (1) Six F/A-18 chase aircraft are available which could be used with the PSFCC; (2) An F/A-18 processor-in-the-loop simulation exists for validation testing; (3) The expertise has been developed in programming the research processor in the PSFCC; and (4) A well-defined process has been established for clearing flight control research projects for flight. This report presents a functional description of the PSFCC. Descriptions of the NASA DFRC facilities, PSFCC verification and validation process, and planned PSFCC projects are also provided.

Carter, John F.↗
NASA NTRS2004

Software Processes SAR Motion-Measurement Data

Motion Measurement Processor (MMP) is one of three computer programs that are used together in the operation of a terrain-mapping dual-frequency interferometric synthetic-aperture-radar (SAR) system. The other two programs - Jurassicprok and Calibration Processor - are described in the two immediately preceding articles. MMP acquires all the motion and attitude data collected by onboard instrumentation systems, including radar, laser and camera metrology, inertial navigation systems, and Global Positioning System (GPS) receivers. MMP combines all this information and processes it into all the trajectory information needed to run Jurassicprok, which performs the interferometric processing and mapping functions. MMP includes several Kalman filters for combining and smoothing aircraft motion and attitude data, and least-squares inversion and filtering software tools for solving for interferometric baseline lengths. MMP synchronizes the motion and radar data. It combines the various measurement data into a unified, seven-dimensional reference system and puts out the resulting filtered trajectory and attitude data along with instructions for use of the data by Jurassicprok, as well as the command files used to operate Jurassicprok.

Freedman, Adam↗
NASA NTRS2018

Range and Intensity Image-Based Terrain and Vehicle Relative Pose Estimation System

A navigation system includes an image acquisition device for acquiring a range image of a target vehicle, at least one processor, a memory including a target vehicle model and computer readable program code, where the processor and the computer readable program code are configured to cause the navigation system to convert the range image to a point cloud having three dimensions, compute a transform from the target vehicle model to the point cloud, and use the transform to estimate the target vehicle's attitude and position for capturing the target vehicle.

Gill, Nathaniel↗
NASA NTRS1991

Distributed memory compiler methods for irregular problems: Data copy reuse and runtime partitioning

Outlined here are two methods which we believe will play an important role in any distributed memory compiler able to handle sparse and unstructured problems. We describe how to link runtime partitioners to distributed memory compilers. In our scheme, programmers can implicitly specify how data and loop iterations are to be distributed between processors. This insulates users from having to deal explicitly with potentially complex algorithms that carry out work and data partitioning. We also describe a viable mechanism for tracking and reusing copies of off-processor data. In many programs, several loops access the same off-processor memory locations. As long as it can be verified that the values assigned to off-processor memory locations remain unmodified, we show that we can effectively reuse stored off-processor data. We present experimental data from a 3-D unstructured Euler solver run on iPSC/860 to demonstrate the usefulness of our methods.

Das, Raja↗
NASA NTRS1982

Step-oriented pipeline data processing system

Architecture for step-oriented pipeline data processing is disclosed utilizing a plurality of cascaded modules, each module including a programmable general purpose processor and a read/write random access memory. The memory of each module, shared with the next module in cascade serves as an output memory for the processor and the input memory for the next processor. An additional memory is provided to serve as the input memory of the first module, and each module is provided with a memory, which may be a read-out memory, to store a program for the processor. Each module is further provided with a logic network for resolving a potential memory sharing conflict by awarding priority to the processor of the module.

Castleman, Kenneth R.↗
NASA NTRS1971

The Advanced On-board Processor (AOP)

The goal of the Advanced On-Board Processor (AOP) development program is to design, build, and flight qualify a highly reliable, moderately priced, digital computer for application on a variety of spacecraft. Included in this development program is the preparation of a complete support software package which consists of an assembler, simulator, loader, system diagnostic, operational executive, and many useful subroutines. The AOP hardware/software system is an extension of the On-Board Processor (OBP) which was developed for general purpose use on earth orbiting spacecraft with its initial application being on-board the fourth Orbiting Astronomical Observatory (OAO-C). Although the OBP possesses the significant features that are required for space application, however, when operating at 100% duty cycle the OBP is too power-consuming for use on many smaller spacecraft. Computer volume will be minimized by implementing the processor and input/output portions of the machine with large scale integrated circuits. Power consumption will be reduced through the use of plated wire and, in some cases, semiconductor memory elements.

Hartenstein, R. G.↗
NASA NTRS1995

Design of a real-time wind turbine simulator using a custom parallel architecture

The design of a new parallel-processing digital simulator is described. The new simulator has been developed specifically for analysis of wind energy systems in real time. The new processor has been named: the Wind Energy System Time-domain simulator, version 3 (WEST-3). Like previous WEST versions, WEST-3 performs many computations in parallel. The modules in WEST-3 are pure digital processors, however. These digital processors can be programmed individually and operated in concert to achieve real-time simulation of wind turbine systems. Because of this programmability, WEST-3 is very much more flexible and general than its two predecessors. The design features of WEST-3 are described to show how the system produces high-speed solutions of nonlinear time-domain equations. WEST-3 has two very fast Computational Units (CU's) that use minicomputer technology plus special architectural features that make them many times faster than a microcomputer. These CU's are needed to perform the complex computations associated with the wind turbine rotor system in real time. The parallel architecture of the CU causes several tasks to be done in each cycle, including an IO operation and the combination of a multiply, add, and store. The WEST-3 simulator can be expanded at any time for additional computational power. This is possible because the CU's interfaced to each other and to other portions of the simulation using special serial buses. These buses can be 'patched' together in essentially any configuration (in a manner very similar to the programming methods used in analog computation) to balance the input/ output requirements. CU's can be added in any number to share a given computational load. This flexible bus feature is very different from many other parallel processors which usually have a throughput limit because of rigid bus architecture.

Hoffman, John A.↗
NASA NTRS1983

Array processor architecture

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Barnes, George H.↗
NASA NTRS1987

Programming methodology for a general purpose automation controller

The General Purpose Automation Controller is a multi-processor architecture for automation programming. A methodology has been developed whose aim is to simplify the task of programming distributed real-time systems for users in research or manufacturing. Programs are built by configuring function blocks (low-level computations) into processes using data flow principles. These processes are activated through the verb mechanism. Verbs are divided into two classes: those which support devices, such as robot joint servos, and those which perform actions on devices, such as motion control. This programming methodology was developed in order to achieve the following goals: (1) specifications for real-time programs which are to a high degree independent of hardware considerations such as processor, bus, and interconnect technology; (2) a component approach to software, so that software required to support new devices and technologies can be integrated by reconfiguring existing building blocks; (3) resistance to error and ease of debugging; and (4) a powerful command language interface.

Sturzenbecker, M. C.↗
NASA NTRS1985

Partitioning problems in parallel, pipelined and distributed computing

The problem of optimally assigning the modules of a parallel program over the processors of a multiple computer system is addressed. A Sum-Bottleneck path algorithm is developed that permits the efficient solution of many variants of this problem under some constraints on the structure of the partitions. In particular, the following problems are solved optimally for a single-host, multiple satellite system: partitioning multiple chain structured parallel programs, multiple arbitrarily structured serial programs and single tree structured parallel programs. In addition, the problems of partitioning chain structured parallel programs across chain connected systems and across shared memory (or shared bus) systems are also solved under certain constraints. All solutions for parallel programs are equally applicable to pipelined programs. These results extend prior research in this area by explicitly taking concurrency into account and permit the efficient utilization of multiple computer architectures for a wide range of problems of practical interest.

Bokhari, S.↗
NASA NTRS1979

SPAR thermal analysis processors reference manual, system level 16. Volume 1: Program executive. Volume 2: Theory. Volume 3: Demonstration problems. Volume 4: Experimental thermal element capability. Volume 5: Programmer reference

User instructions are given for performing linear and nonlinear steady state and transient thermal analyses with SPAR thermal analysis processors TGEO, SSTA, and TRTA. It is assumed that the user is familiar with basic SPAR operations and basic heat transfer theory.

Marlowe, M. B.↗
NASA NTRS1978

Formulation of consumables management models. Volume 1: Mission planning

Development of an STS (Space Transportation System) interactive computer program MPP (Mission Planning Processor) working model was conducted. A summary of the computer program development and those supporting tasks conducted is presented. Development of the MPP Computer Program is discussed. This development was supported by several parallel tasks. These tasks either directly supported the program development, or provided information for future application and/or modification to the program in relation to the flight planning and flight operations of the STS and advanced spacecraft. The supporting tasks also included development of a Space Station MPP to demonstrate the applicability of the analytical methods developed under this RTOP to more advanced spacecraft than the STS.

Torian, J. G.↗
NASA NTRS1988

Partitioning problems in parallel, pipelined, and distributed computing

The problem of optimally assigning the modules of a parallel program over the processors of a multiple-computer system is addressed. A sum-bottleneck path algorithm is developed that permits the efficient solution of many variants of this problem under some constraints on the structure of the partitions. In particular, the following problems are solved optimally for a single-host, multiple-satellite system: partitioning multiple chain-structured parallel programs, multiple arbitrarily structured serial programs, and single-tree structured parallel programs. In addition, the problem of partitioning chain-structured parallel programs across chain-connected systems is solved under certain constraints. All solutions for parallel programs are equally applicable to pipelined programs. These results extend prior research in this area by explicitly taking concurrency into account and permit the efficient utilization of multiple-computer architectures for a wide range of problems of practical interest.

Bokhari, Shahid H.↗
NASA NTRS1994

Advanced information processing system: The Army Fault-Tolerant Architecture detailed design overview

The Army Avionics Research and Development Activity (AVRADA) is pursuing programs that would enable effective and efficient management of large amounts of situational data that occurs during tactical rotorcraft missions. The Computer Aided Low Altitude Night Helicopter Flight Program has identified automated Terrain Following/Terrain Avoidance, Nap of the Earth (TF/TA, NOE) operation as key enabling technology for advanced tactical rotorcraft to enhance mission survivability and mission effectiveness. The processing of critical information at low altitudes with short reaction times is life-critical and mission-critical necessitating an ultra-reliable/high throughput computing platform for dependable service for flight control, fusion of sensor data, route planning, near-field/far-field navigation, and obstacle avoidance operations. To address these needs the Army Fault Tolerant Architecture (AFTA) is being designed and developed. This computer system is based upon the Fault Tolerant Parallel Processor (FTPP) developed by Charles Stark Draper Labs (CSDL). AFTA is hard real-time, Byzantine, fault-tolerant parallel processor which is programmed in the ADA language. This document describes the results of the Detailed Design (Phase 2 and 3 of a 3-year project) of the AFTA development. This document contains detailed descriptions of the program objectives, the TF/TA NOE application requirements, architecture, hardware design, operating systems design, systems performance measurements and analytical models.

Harper, Richard E.↗
NASA NTRS2012

From EXOSAT to the High Energy Astrophysics Science Archive (HEASARC): X-ray Astronomy Comes of Age

In May 1983 the European Space Agency launched EXOSAT, its first X-ray astronomy observatory. Even though it lasted only 3 short years, this mission brought not only new capabilities that resulted in unexpected discoveries, but also a pioneering approach to operations and archiving that changed X-ray astronomy from observations led by small instrument teams, to an observatory approach open to the entire community through a guest observer program. The community use of the observatory was supported by a small dedicated team of scientists, the precursor to the data center activities created to support e.g. Chandra and XMM-Newton. The new science capabilities of EX OS AT included a 90 hr highly eccentric high earth orbit that allow unprecedented continuous coverage of sources as well as direct communication with the satellite that allowed real time decisions to respond to unexpected events through targets of opportunity. The advantages of this orbit demonstrated by EXOSAT resulted in Chandra and XMM-Newton selecting similar orbits. The three instruments on board the EXOSAT observatory were complementary, designed to give complete coverage over a wide energy band pass of 0.05-50 keY. An onboard processor could be programmed to give multiple data modes that could be optimized in response to science discoveries: These new capabilities resulted in many new discoveries including the first comprehensive study of AGN variability, new orbital periods in X-ray binaries and cataclysmic variables, new black holes, quasi-periodic oscillations from neutron stars and black holes and broad band X-ray spectroscopy. The EXOSAT team generated a well-organized database accessible worldwide over the nascent internet, allowing remote selection of data products, making samples and undertaking surveys from the data. The HEASARC was established by NASA at Goddard Space Flight Center in 1990 as the repository of NASA X-ray and Gamma-ray data. The proven EXOSAT database system became the core of the HEASARC infrastructure. The HEASARC pioneered many concepts now taken for granted including standardized formats using FITS files, restoring data from earlier missions, multi-mission analysis tools and a searchable archive over the world wide web.

White, Nicholas E.↗
NASA NTRS1970

Time Data Sequential Processor /TDSP/

Time Data Sequential Processor /TDSP/ computer program provides preflight predictions for lunar trajectories from injection to impact, and for planetary escape trajectories for up to 100 hours from launch. One of the major options TDSP performs is the determination of tracking station view periods.

Joseph, A. E.↗
NASA NTRS1987

Real time animation of space plasma phenomena

In pursuit of real time animation of computer simulated space plasma phenomena, the code was rewritten for the Massively Parallel Processor (MPP). The program creates a dynamic representation of the global bowshock which is based on actual spacecraft data and designed for three dimensional graphic output. This output consists of time slice sequences which make up the frames of the animation. With the MPP, 16384, 512 or 4 frames can be calculated simultaneously depending upon which characteristic is being computed. The run time was greatly reduced which promotes the rapid sequence of images and makes real time animation a foreseeable goal. The addition of more complex phenomenology in the constructed computer images is now possible and work proceeds to generate these images.

Jordan, K. F.↗