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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Concurrent processing adaptation of aeroelastic analysis of propfans

Discussed here is a study involving the adaptation of an advanced aeroelastic analysis program to run concurrently on a shared memory multiple processor computer. The program uses a three-dimensional compressible unsteady aerodynamic model and blade normal modes to calculate aeroelastic stability and response of propfan blades. The identification of the computational parallelism within the sequential code and the scheduling of the concurrent subtasks to minimize processor idle time are discussed. Processor idle time in the calculation of the unsteady aerodynamic coefficients was reduced by the simple strategy of appropriately ordering the computations. Speedup and efficiency results are presented for the calculation of the matched flutter point of an experimental propfan model. The results show that efficiencies above 70 percent can be obtained using the present implementation with 7 processors. The parallel computational strategy described here is also applicable to other aeroelastic analysis procedures based on panel methods.

Murthy, D. V.↗
NASA NTRSDate not supplied

Diving into the Data Plane of Delay Tolerant Networks

This presentation details early research towards applying data plane programming and software defined networking (SDN) to delay tolerant networking (DTN). This involved using the Programming Protocol-Independent Packet Processors (P4) language to program the data plane to handle DTN bundles natively in hardware. The results presented include a proof of concept DTN Bundle Protocol (BP) translator network middlebox, the challenges of programming a data plane to process BP, a software-defined DTN (SDDTN) architecture, and potential future applications of SDDTN. It is demonstrated that SDN and the P4 language has high potential for improving the scalability of DTN networks, although further research must be done to enable this.

Dominick Ta↗
NASA NTRS1986

Approximate algorithms for partitioning and assignment problems

The problem of optimally assigning the modules of a parallel/pipelined program over the processors of a multiple computer system under certain restrictions on the interconnection structure of the program as well as the multiple computer system was considered. For a variety of such programs it is possible to find linear time if a partition of the program exists in which the load on any processor is within a certain bound. This method, when combined with a binary search over a finite range, provides an approximate solution to the partitioning problem. The specific problems considered were: a chain structured parallel program over a chain-like computer system, multiple chain-like programs over a host-satellite system, and a tree structured parallel program over a host-satellite system. For a problem with m modules and n processors, the complexity of the algorithm is no worse than O(mnlog(W sub T/epsilon)), where W sub T is the cost of assigning all modules to one processor and epsilon the desired accuracy.

Iqbal, M. A.↗
NASA NTRS1995

Program Processes Thermocouple Readings

Digital Signal Processor for Thermocouples (DART) computer program implements precise and fast method of converting voltage to temperature for large-temperature-range thermocouple applications. Written using LabVIEW software. DART available only as object code for use on Macintosh II FX or higher-series computers running System 7.0 or later and IBM PC-series and compatible computers running Microsoft Windows 3.1. Macintosh version of DART (SSC-00032) requires LabVIEW 2.2.1 or 3.0 for execution. IBM PC version (SSC-00031) requires LabVIEW 3.0 for Windows 3.1. LabVIEW software product of National Instruments and not included with program.

Quave, Christine A.↗
NASA NTRS1976

Real-time video compression algorithm for Hadamard transform processing

A real-time digital video processor using Hadamard transform techniques to reduce video bandwidth is described. The processor can be programmed with different parameters to investigate various algorithms for bandwidth compression. The processor is also adaptive in that it can select different parameter sets to tradeoff spatial resolution for temporal resolution in the regions of the picture that are moving. Algorithms used in programming the system are described along with results achieved at various levels of compression. The algorithms relate to spatial compression, temporal compression, and the adaptive selection of parameter sets.

Knauer, S. C.↗
NASA NTRS1975

Real-time video compression algorithm for Hadamard transform processing

A real-time digital video processor using Hadamard transform techniques to reduce video bandwidth is described. The processor can be programmed with different parameters to investigate various algorithms for bandwidth compression. The processor is also adaptive in that it can select different parameter sets to trade off spatial resolution for temporal resolution in the regions of the picture that are moving. Algorithms used in programming the system are described along with results achieved at various levels of compression. The algorithms relate to spatial compression, temporal compression, and the adaptive selection of parameter sets.

Knauer, S. C.↗
NASA NTRS1988

An intelligent allocation algorithm for parallel processing

The problem of allocating nodes of a program graph to processors in a parallel processing architecture is considered. The algorithm is based on critical path analysis, some allocation heuristics, and the execution granularity of nodes in a program graph. These factors, and the structure of interprocessor communication network, influence the allocation. To achieve realistic estimations of the executive durations of allocations, the algorithm considers the fact that nodes in a program graph have to communicate through varying numbers of tokens. Coarse and fine granularities have been implemented, with interprocessor token-communication duration, varying from zero up to values comparable to the execution durations of individual nodes. The effect on allocation of communication network structures is demonstrated by performing allocations for crossbar (non-blocking) and star (blocking) networks. The algorithm assumes the availability of as many processors as it needs for the optimal allocation of any program graph. Hence, the focus of allocation has been on varying token-communication durations rather than varying the number of processors. The algorithm always utilizes as many processors as necessary for the optimal allocation of any program graph, depending upon granularity and characteristics of the interprocessor communication network.

Carroll, Chester C.↗
NASA NTRS1974

The engineering design integration (EDIN) system

A digital computer program complex for the evaluation of aerospace vehicle preliminary designs is described. The system consists of a Univac 1100 series computer and peripherals using the Exec 8 operating system, a set of demand access terminals of the alphanumeric and graphics types, and a library of independent computer programs. Modification of the partial run streams, data base maintenance and construction, and control of program sequencing are provided by a data manipulation program called the DLG processor. The executive control of library program execution is performed by the Univac Exec 8 operating system through a user established run stream. A combination of demand and batch operations is employed in the evaluation of preliminary designs. Applications accomplished with the EDIN system are described.

Glatt, C. R.↗
NASA NTRS1996

On Board Processor Development for NASA's Advanced Radar Technology Program

This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications on custom hardware, and consideration on implementation approaches. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.

SAR radar on-board processing spacecraft mapping i↗
NASA NTRS1997

Production Support Flight Control Computers: Research Capability for F/A-18 Aircraft at Dryden Flight Research Center

NASA Dryden Flight Research Center (DFRC) is working with the United States Navy to complete ground testing and initiate flight testing of a modified set of F/A-18 flight control computers. The Production Support Flight Control Computers (PSFCC) can give any fleet F/A-18 airplane an in-flight, pilot-selectable research control law capability. NASA DFRC can efficiently flight test the PSFCC for the following four reasons: (1) Six F/A-18 chase aircraft are available which could be used with the PSFCC; (2) An F/A-18 processor-in-the-loop simulation exists for validation testing; (3) The expertise has been developed in programming the research processor in the PSFCC; and (4) A well-defined process has been established for clearing flight control research projects for flight. This report presents a functional description of the PSFCC. Descriptions of the NASA DFRC facilities, PSFCC verification and validation process, and planned PSFCC projects are also provided.

Carter, John F.↗
NASA NTRS2004

Software Processes SAR Motion-Measurement Data

Motion Measurement Processor (MMP) is one of three computer programs that are used together in the operation of a terrain-mapping dual-frequency interferometric synthetic-aperture-radar (SAR) system. The other two programs - Jurassicprok and Calibration Processor - are described in the two immediately preceding articles. MMP acquires all the motion and attitude data collected by onboard instrumentation systems, including radar, laser and camera metrology, inertial navigation systems, and Global Positioning System (GPS) receivers. MMP combines all this information and processes it into all the trajectory information needed to run Jurassicprok, which performs the interferometric processing and mapping functions. MMP includes several Kalman filters for combining and smoothing aircraft motion and attitude data, and least-squares inversion and filtering software tools for solving for interferometric baseline lengths. MMP synchronizes the motion and radar data. It combines the various measurement data into a unified, seven-dimensional reference system and puts out the resulting filtered trajectory and attitude data along with instructions for use of the data by Jurassicprok, as well as the command files used to operate Jurassicprok.

Freedman, Adam↗
NASA NTRS2018

Range and Intensity Image-Based Terrain and Vehicle Relative Pose Estimation System

A navigation system includes an image acquisition device for acquiring a range image of a target vehicle, at least one processor, a memory including a target vehicle model and computer readable program code, where the processor and the computer readable program code are configured to cause the navigation system to convert the range image to a point cloud having three dimensions, compute a transform from the target vehicle model to the point cloud, and use the transform to estimate the target vehicle's attitude and position for capturing the target vehicle.

Gill, Nathaniel↗
NASA NTRS1991

Distributed memory compiler methods for irregular problems: Data copy reuse and runtime partitioning

Outlined here are two methods which we believe will play an important role in any distributed memory compiler able to handle sparse and unstructured problems. We describe how to link runtime partitioners to distributed memory compilers. In our scheme, programmers can implicitly specify how data and loop iterations are to be distributed between processors. This insulates users from having to deal explicitly with potentially complex algorithms that carry out work and data partitioning. We also describe a viable mechanism for tracking and reusing copies of off-processor data. In many programs, several loops access the same off-processor memory locations. As long as it can be verified that the values assigned to off-processor memory locations remain unmodified, we show that we can effectively reuse stored off-processor data. We present experimental data from a 3-D unstructured Euler solver run on iPSC/860 to demonstrate the usefulness of our methods.

Das, Raja↗
NASA NTRS1982

Step-oriented pipeline data processing system

Architecture for step-oriented pipeline data processing is disclosed utilizing a plurality of cascaded modules, each module including a programmable general purpose processor and a read/write random access memory. The memory of each module, shared with the next module in cascade serves as an output memory for the processor and the input memory for the next processor. An additional memory is provided to serve as the input memory of the first module, and each module is provided with a memory, which may be a read-out memory, to store a program for the processor. Each module is further provided with a logic network for resolving a potential memory sharing conflict by awarding priority to the processor of the module.

Castleman, Kenneth R.↗
NASA NTRS1971

The Advanced On-board Processor (AOP)

The goal of the Advanced On-Board Processor (AOP) development program is to design, build, and flight qualify a highly reliable, moderately priced, digital computer for application on a variety of spacecraft. Included in this development program is the preparation of a complete support software package which consists of an assembler, simulator, loader, system diagnostic, operational executive, and many useful subroutines. The AOP hardware/software system is an extension of the On-Board Processor (OBP) which was developed for general purpose use on earth orbiting spacecraft with its initial application being on-board the fourth Orbiting Astronomical Observatory (OAO-C). Although the OBP possesses the significant features that are required for space application, however, when operating at 100% duty cycle the OBP is too power-consuming for use on many smaller spacecraft. Computer volume will be minimized by implementing the processor and input/output portions of the machine with large scale integrated circuits. Power consumption will be reduced through the use of plated wire and, in some cases, semiconductor memory elements.

Hartenstein, R. G.↗
NASA NTRS1995

Design of a real-time wind turbine simulator using a custom parallel architecture

The design of a new parallel-processing digital simulator is described. The new simulator has been developed specifically for analysis of wind energy systems in real time. The new processor has been named: the Wind Energy System Time-domain simulator, version 3 (WEST-3). Like previous WEST versions, WEST-3 performs many computations in parallel. The modules in WEST-3 are pure digital processors, however. These digital processors can be programmed individually and operated in concert to achieve real-time simulation of wind turbine systems. Because of this programmability, WEST-3 is very much more flexible and general than its two predecessors. The design features of WEST-3 are described to show how the system produces high-speed solutions of nonlinear time-domain equations. WEST-3 has two very fast Computational Units (CU's) that use minicomputer technology plus special architectural features that make them many times faster than a microcomputer. These CU's are needed to perform the complex computations associated with the wind turbine rotor system in real time. The parallel architecture of the CU causes several tasks to be done in each cycle, including an IO operation and the combination of a multiply, add, and store. The WEST-3 simulator can be expanded at any time for additional computational power. This is possible because the CU's interfaced to each other and to other portions of the simulation using special serial buses. These buses can be 'patched' together in essentially any configuration (in a manner very similar to the programming methods used in analog computation) to balance the input/ output requirements. CU's can be added in any number to share a given computational load. This flexible bus feature is very different from many other parallel processors which usually have a throughput limit because of rigid bus architecture.

Hoffman, John A.↗