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At least 109 records · Page 6

Low-loss interconnects for modular superconducting quantum processors

Low-loss superconducting aluminium cables and on-chip impedance transformers can be used to link qubit modules and create superconducting quantum computing networks with high-fidelity intermodule state transfer. Scaling is now a key challenge in superconducting quantum computing. One solution is to build modular systems in which smaller-scale quantum modules are individually constructed and calibrated and then assembled into a larger architecture. This, however, requires the development of suitable interconnects. Here we report low-loss interconnects based on pure aluminium coaxial cables and on-chip impedance transformers featuring quality factors of up to 8.1 x 10 5 , which is comparable with the performance of our transmon qubits fabricated on a single-crystal sapphire substrate. We use these interconnects to link five quantum modules with intermodule quantum state transfer and Bell state fidelities of up to 99%. To benchmark the overall performance of the processor, we create maximally entangled, multiqubit Greenberger-Horne-Zeilinger states. The generated intermodule four-qubit Greenberger-Horne-Zeilinger state exhibits 92.0% fidelity. We also entangle up to 12 qubits in a Greenberger-Horne-Zeilinger state with 55.8 ± 1.8% fidelity, which is above the genuine multipartite entanglement threshold of 1/2.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

An Artificial Retina Processor for Track Reconstruction at the LHC Crossing Rate

The goal of the INFN-RETINA R&D project is to develop and implement a computational methodology that allows to reconstruct events with a large number (> 100) of charged-particle tracks in pixel and silicon strip detectors at 40 MHz, thus matching the requirements for processing LHC events at the full bunch-crossing frequency. Our approach relies on a parallel pattern-recognition algorithm, dubbed artificial retina, inspired by the early stages of image processing by the brain. In order to demonstrate that a track-processing system based on this algorithm is feasible, we built a sizable prototype of a tracking processor tuned to 3 000 patterns, based on already existing readout boards equipped with Altera Stratix III FPGAs. The detailed geometry and charged-particle activity of a large tracking detector currently in operation are used to assess its performances. We report on the test results with such a prototype.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

The CMS Barrel Calorimeter Processor demonstrator (BCPv1) board evaluation

For the CERN LHC phase 2, the barrel region of the CMS electromagnetic (ECAL EB) and hadronic calorimeters (HCAL HB) require new back-end electronics for their readout. To this purpose, a first version of the ATCA-based blade, the Barrel Calorimeter Processor (BCPv1), has been developed. The performance of the optical links as well as clock distribution are also presented here. Here, the BCPv1 has been tested together with front-end and trigger boards, as well as with the new DAQ and TCDS Hub (DTH) [1], to demonstrate that the BCPv1 meets the required specifications.

47 OTHER INSTRUMENTATION↗

Co-designing Spectral Transformation Oracles with Hybrid Oscillator-Qubit Quantum Processors: From Algorithms to Compilation

We co-design a family of quantum eigenvalue transformation oracles that can be efficiently implemented on hybrid discrete- or continuous-variable (qubit or qumode) hardware. To illustrate the oracle’s representation-theoretic power and near-term experimental accessibility, we encode a Gaussian imaginary time-evolution spectral filter. As a result, we define a continuous linear combination of unitaries block encoding. Due to the ancillary qumode’s infinite-dimensional nature, continuous-variable qumodes constitute a powerful compilation tool for encoding continuous spectral functions without discretization errors while minimizing resource requirements. We then focus on the ubiquitous task of preparing eigenstates in quantum spin models. For completeness, we provide an end-to-end compilation which expresses high-level oracles in terms of an experimentally realizable instruction set architecture in both 1D and 2D. Finally, we examine the leading-order effects of physical errors and highlight open research directions. Our algorithms scale linearly with the spatial extent of the target system and are applicable to both near-term and large-scale quantum processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Quantum criticality using a superconducting quantum processor

Quantum criticality emerges from the collective behavior of many interacting quantum particles, often at the transition between different phases of matter. It is one of the cornerstones of condensed matter physics, which we access on noisy intermediate-scale (NISQ) quantum devices by leveraging a dynamically driven phenomenon. Here we probe the critical properties of the one-dimensional quantum Ising model on a programmable superconducting quantum chip via a Kibble-Zurek process, obtain scaling laws, and estimate critical exponents despite inherent sources of errors on the hardware. In addition, we investigate how the improvement of NISQ computers (more qubits, less noise) will consolidate the computation of those universal physical properties. A one-parameter noise model captures the effect of imperfections and reproduces the experimental data. Its systematic study reveals that the noise, analogously to temperature, induces a new length scale in the system. We introduce and successfully verify modified scaling laws, directly accounting for the noise without any prior knowledge. It makes data analyses for extracting physical properties transparent to noise. By understanding how imperfect quantum hardware modifies the genuine properties of quantum states of matter, we enhance the power of NISQ processors considerably for addressing quantum criticality and potentially other phenomena and algorithms.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Qudit Dynamical Decoupling on a Superconducting Quantum Processor

Multilevel qudit systems are increasingly being explored as alternatives to traditional qubit systems due to their denser information storage and processing potential. However, qudits are more susceptible to decoherence than qubits due to increased loss channels, noise sensitivity, and crosstalk. To address these challenges, we develop protocols for dynamical decoupling (DD) of qudit systems based on the Heisenberg-Weyl group. We implement and experimentally verify these DD protocols on a superconducting transmon processor that supports qudit operation based on qutrits (d = 3) and ququarts (d = 4). Specifically, we demonstrate single-qudit DD sequences to decouple qutrits and ququarts from system-bath-induced decoherence. Here we also introduce two-qudit DD sequences designed to suppress the detrimental cross-Kerr couplings between coupled qudits. This allows us to demonstrate a significant improvement in the fidelity of time-evolved qutrit Bell states. Our results highlight the utility of leveraging DD to enable scalable qudit-based quantum computing.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Toward coherent quantum computation of scattering amplitudes with a measurement-based photonic quantum processor

In recent years, applications of quantum simulation have been developed to study the properties of strongly interacting theories. This has been driven by two factors: on the one hand, needs from theorists to have access to physical observables that are prohibitively difficult to study using classical computing; on the other hand, quantum hardware becoming increasingly reliable and scalable to larger systems. In this work, we discuss the feasibility of using quantum optical simulation for studying scattering observables that are presently inaccessible via lattice QCD and are at the core of the experimental program at Jefferson Laboratory, the future Electron-Ion Collider, and other accelerator facilities. We show that recent progress in measurement-based photonic quantum computing can be leveraged to provide deterministic generation of required exotic gates and implementation in a single photonic quantum processor. Published by the American Physical Society 2024

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

Vulnerability Detection Methodology for a Digital Signal Processor Micro-Controller at Edge Level Distributed Energy Resource Controller

Integration of renewable energy and energy storage based Distributed Energy Resource (DER) assets to the grid has seen an upsurge over the past few decades. Traditionally, energy would be generated at a thermal or nuclear power plant and then transmitted over long distance through the transmission grid and then supply to the customers at the distribution grid. Modern renewable energy based DER assets have brought energy production at the edge of distribution grid, which has made the grid vulnerable to cyber intrusion as the power flow controllers for such DER assets are now distributed across the grid from distribution level to transmission level. This paper discusses the vulnerability posed by such power flow controllers of DER assets and demonstrates a detection methodology for unauthorized access and manipulation of system configuration for Digital Signal Processor based Microcontrollers. Experimental results proving efficacy of the methodology have been shown in paper.

Bhowmik, Pankaj↗

Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization

Continuing the scaling of quantum computers hinges on building classical control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the control processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. Here, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O(10 2 ) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.

97 MATHEMATICS AND COMPUTING↗

All-Optical Frequency Processor for Networking Applications

Herein, we propose an electro-optic approach for transparent optical networking, in which frequency channels are actively transformed into any desired mapping in a wavelength-multiplexed environment. Based on electro-optic phase modulators and Fourier-transform pulse shapers, our all-optical frequency processor (AFP) is examined numerically for the specific operations of frequency channel hopping and broadcasting, and found capable of implementing these transformations with favorable component requirements. Extending our analysis via a mutual-information–based metric for system optimization, we show how to optimize transformation performance under limited resources in a classical context, contrasting the results with those found using metrics motivated by quantum information, such as fidelity and success probability. Given its compatibility with on-chip implementation, as well as elimination of optical-to-electrical conversion in frequency channel switching, the AFP looks to offer valuable potential in silicon photonic network design, as well as the realization of high-dimensional frequency-bin gates.

42 ENGINEERING↗

Peptide Hit Results Processor

The Peptide Hit Results Processor (PHRP) can be used to convert an X!Tandem results file (XML format), MSGF+ .tsv search result file, Sequest Synopsis/First Hits file, or Inspect search result into a series of tab-delimited text files summarizing the results. It will insert modification symbols into the peptide sequences for modified peptides. Parallel files are created containing sequence information, modification details, and protein information. The user can optionally provide a modification definition file that specifies the symbol to use for each modification mass.

Gibbons, Bryson↗

Workbench Analysis Sequence Processor

The Workbench Analysis Sequence Processor (WASP) was developed to streamline lexing, parsing, access, validation, and analysis of ascii text files.

Lefebvre, RobertA.↗

High-dimensional discrete Fourier transform gates with a quantum frequency processor

The discrete Fourier transform (DFT) is of fundamental interest in photonic quantum information, yet the ability to scale it to high dimensions depends heavily on the physical encoding, with practical recipes lacking in emerging platforms such as frequency bins. In this article, we show that d -point frequency-bin DFTs can be realized with a fixed three-component quantum frequency processor (QFP), simply by adding to the electro-optic modulation signals one radio-frequency harmonic per each incremental increase in d . We verify gate fidelity F W > 0.9997 and success probability P W > 0.965 up to d = 10 in numerical simulations, and experimentally implement the solution for d = 3, utilizing measurements with parallel DFTs to quantify entanglement and perform tomography of multiple two-photon frequency-bin states. Our results furnish new opportunities for high-dimensional frequency-bin protocols in quantum communications and networking.

97 MATHEMATICS AND COMPUTING↗

Dosimetry Processor v1.0 User's Manual

The following discussion contains a detailed description of how to interface and operate Dosimetry Processor v1.0 software application. It describes the input required from the user to process dosimetry and actions to take for troubleshooting.

97 MATHEMATICS AND COMPUTING↗

Metrics and Benchmarks for Quantum Processors: State of Play

A compelling narrative has taken hold as quantum computing explodes into the commercial sector: Quantum computing in 2018 is like classical computing in 1965. In 1965 Gordon Moore wrote his famous paper about integrated circuits, saying: "At present, [minimum cost] is reached when 50 components are used per circuit. But... the complexity for minimum component costs has increased at a rate of roughly a factor of two per year... by 1975, the number of components per integrated circuit for minimum cost will be 65,000." This narrative is both appealing (we want to believe that quantum computing will follow the incredibly successful path of classical computing!) and plausible (2018 saw IBM, Intel, and Google announce 50-qubit integrated chips). But it is also deeply misleading. Here is an alternative: Quantum computing in 2018 is like classical computing in 1938. In 1938, John Atanasoff and Clifford Berry built the very first electronic digital computer. It had no program, and was not Turing-complete. Vacuum tubes — the standard "bit" for 20 years — were still 5 years in the future. ENIAC and the achievement of "computational supremacy" (over hand calculation) wouldn't arrive for 8 years, despite the accelerative effect of WWII. Integrated circuits and the information age were more than 20 years away. Neither of these analogies is perfect. Quantum computing technology is more like 1938, while the level of funding and excitement suggest 1965 (or later!). But the point of the cautionary analogy to 1938 is simple: Quantum computing in 2018 is a research field. It is far too early to establish metrics or benchmarks for performance. The best role for neutral organizations like IEEE is to encourage and shape research into metrics and benchmarks, so as to be ready when they become necessary. This white paper presents the evidence and reasoning for this claim. We explain what it means to say that quantum computing is a "research field", and why metrics and benchmarks for quantum processors also constitute a research field. We discuss the potential for harmful consequences of prematurely establishing standards or frameworks. We conclude by suggesting specific actions that IEEE or similar organizations can take to accelerate the development of good metrics and benchmarks for quantum computing.

97 MATHEMATICS AND COMPUTING↗

Workbench Analysis Sequence Processor

The Workbench Analysis Sequence Processor (WASP) was developed to streamline lexing, parsing, access, validation, and analysis of ascii text files. The foundation of WASP resides on the parse tree data structure, where each node in the tree represents the syntax of the input document. Nodes can parent nodes with children. Nodes that have no children are known as terminal or leaf nodes , and they represent tokens (string, number, delimiter, etc.) in the text file. The fast lexical analyzer generator (flex - https://www.gnu.org/software/flex/) and GNU Bison parser generator (https://www.gnu.org/software/bison/) are extensively used for lexing and parsing.

97 MATHEMATICS AND COMPUTING↗