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At least 109 records · Page 6

Parallel-vector unsymmetric Eigen-Solver on high performance computers

The popular QR algorithm for solving all eigenvalues of an unsymmetric matrix is reviewed. Among the basic components in the QR algorithm, it was concluded from this study, that the reduction of an unsymmetric matrix to a Hessenberg form (before applying the QR algorithm itself) can be done effectively by exploiting the vector speed and multiple processors offered by modern high-performance computers. Numerical examples of several test cases have indicated that the proposed parallel-vector algorithm for converting a given unsymmetric matrix to a Hessenberg form offers computational advantages over the existing algorithm. The time saving obtained by the proposed methods is increased as the problem size increased.

Nguyen, Duc T.↗

OPAD-EDIFIS Real-Time Processing

The Optical Plume Anomaly Detection (OPAD) detects engine hardware degradation of flight vehicles through identification and quantification of elemental species found in the plume by analyzing the plume emission spectra in a real-time mode. Real-time performance of OPAD relies on extensive software which must report metal amounts in the plume faster than once every 0.5 sec. OPAD software previously written by NASA scientists performed most necessary functions at speeds which were far below what is needed for real-time operation. The research presented in this report improved the execution speed of the software by optimizing the code without changing the algorithms and converting it into a parallelized form which is executed in a shared-memory multiprocessor system. The resulting code was subjected to extensive timing analysis. The report also provides suggestions for further performance improvement by (1) identifying areas of algorithm optimization, (2) recommending commercially available multiprocessor architectures and operating systems to support real-time execution and (3) presenting an initial study of fault-tolerance requirements.

Katsinis, Constantine↗

Digital Control Technologies for Modular DC-DC Converters

Recent trends in aerospace Power Management and Distribution (PMAD) systems focus on using commercial off-the-shelf (COTS) components as standard building blocks. This move to more modular designs has been driven by a desire to reduce costs and development times, but is also due to the impressive power density and efficiency numbers achieved by today's commercial DC-DC converters. However, the PMAD designer quickly learns of the hidden "costs" of using COTS converters. The most significant cost is the required addition of external input filters to meet strict electromagnetic interference (MIAMI) requirements for space systems. In fact, the high power density numbers achieved by the commercial manufacturers are greatly due to the lack of necessary input filters included in the COTS module. The NASA Glenn Research Center is currently pursuing a digital control technology that addresses this problem with modular DC-DC converters. This paper presents the digital control technologies that have been developed to greatly reduce the input filter requirements for paralleled, modular DC-DC converters. Initial test result show that the input filter's inductor size was reduced by 75 percent, and the capacitor size was reduced by 94 percent while maintaining the same power quality specifications.

Button, Robert M.↗

Gigabit Ethernet Asynchronous Clock Compensation FIFO

Clock compensation for Gigabit Ethernet is necessary because the clock recovered from the 1.25 Gb/s serial data stream has the potential to be 200 ppm slower or faster than the system clock. The serial data is converted to 10-bit parallel data at a 125 MHz rate on a clock recovered from the serial data stream. This recovered data needs to be processed by a system clock that is also running at a nominal rate of 125 MHz, but not synchronous to the recovered clock. To cross clock domains, an asynchronous FIFO (first-in-first-out) is used, with the write pointer (wprt) in the recovered clock domain and the read pointer (rptr) in the system clock domain. Because the clocks are generated from separate sources, there is potential for FIFO overflow or underflow. Clock compensation in Gigabit Ethernet is possible by taking advantage of the protocol data stream features. There are two distinct data streams that occur in Gigabit Ethernet where identical data is transmitted for a period of time. The first is configuration, which happens during auto-negotiation. The second is idle, which occurs at the end of auto-negotiation and between every packet. The identical data in the FIFO can be repeated by decrementing the read pointer, thus compensating for a FIFO that is draining too fast. The identical data in the FIFO can also be skipped by incrementing the read pointer, which compensates for a FIFO draining too slowly. The unique and novel features of this FIFO are that it works in both the idle stream and the configuration streams. The increment or decrement of the read pointer is different in the idle and compensation streams to preserve disparity. Another unique feature is that the read pointer to write pointer difference range changes between compensation and idle to minimize FIFO latency during packet transmission.

Duhachek, Jeff↗

Fundamental Studies of Bifunctional Catalysts for Tandem Reactions

During the past few years of our funding from DOE Basic Energy Sciences, we have focused on the catalytic conversion of biomass-derived 5-hydroxymethyl furfural (HMF) as a platform molecule for sustainable synthesis of value-added chemicals. The combination of the diene and aldehyde functionalities in HMF enables catalytic production of acetalized HMF derivatives with diol or epoxy reactants to allow reversible synthesis of norcantharimide derivatives upon Diels-Alder reaction with maleimides. Whereas the electron-withdrawing nature of aldehyde group inhibits the reactivity of diene group in HMF to undergo Diels-Alder reactions with dienophiles, by converting the aldehyde group in HMF to an electron-donating hydroxyl group, HMF can append maleimide-based chemicals through Diels-Alder coupling. Acetalization of HMF not only produces an electron-rich diene for Diels-Alder reaction, but it also alters the reversibility of acetal formation and thereby allows for the controlled release of chemicals by hydrolysis. Therefore, we synthesized various norcantharimide derivatives from biomass-derived HMF by acetalization over an acid catalyst, Amberlyst-15, followed by Diels-Alder reaction with maleimide. The norcantharimides release the starting materials by retro Diels-Alder reaction that is triggered by acetal hydrolysis under acidic (≤pH 3) conditions. In subsequent work, we explored the synthesis and properties of functional polyurethanes and polyesters with tunable properties from biomass-derived (HMF)-Acetone-HMF (HAH) monomers. HAH can be selectively hydrogenated over Cu and Ru catalysts to produce partially-hydrogenated HAH (PHAH) and fully-hydrogenated HAH (FHAH). HAH contains functional groups, including hydroxyl, furan, enone, and ketone functionalities, that can be exploited to further tune the polymer properties. The π-electron conjugation between the enone and furan groups in HAH monomer stabilizes the furan group to prevent the uncontrolled degradation of furans during reactions, such as etherification. Therefore, HAH is a renewable monomer that can be used to synthesize polymers, having high molecular weight, symmetric functionalities, an inexpensive production price, and being derived from renewable resources without competition with food resources. We demonstrated the synthesis of functional polyurethanes and a renewable polyester from HAH-derived monomers, and 4,4’-methylenebis(phenyl isocyanate) (MDI). We showed that it is essential to be able to selective hydrogenate C=C double bonds in HAH to be able to achieve effective Diels Alder reactions of the furan ring. Therefore, we studied the hydrogenation at temperatures from 313 – 393 K of HAH over Pd, Ru, and Cu based catalysts. HAH was selectively hydrogenated to produce partially-hydrogenated monomers (PHAH) over Cu and Ru catalysts and to fully-hydrogenated HAH monomers (FHAH) over the Ru catalyst. Pd based catalysts yielded a mixture of partially and fully hydrogenated monomers. Reaction kinetics models were employed to quantify the kinetic behavior for hydrogenation over Ru, Cu, and Pd catalysts. A 5-step pathway exhibited over Pd and Ru catalysts consists of both series and parallel reaction steps, where HAH is both converted to fully hydrogenated products sequentially via series reactions of partially hydrogenated intermediates, as well as converted directly in parallel reactions to form the fully hydrogenated products. In contrast, a 3-step pathway over the Cu catalyst consists only of the consecutive reaction steps, where the final product was formed via series reactions of intermediate products. Additionally, reaction over the Cu catalyst did not hydrogenate the furan rings of the HAH molecule and yielded a different final product than those hydrogenation over Pd and Ru catalysts. Using the results from our detailed reaction kinetics studies, we developed universal conditions for the maximum production of the various hydrogenated products for both batch and plug flow systems. In subsequent work, we employed reaction schemes to optimize the yields of products from selective hydrogenations of HAH in isopropanol solvent and in the presence of liquid water. Reaction schemes consisting of 7, 9, and 11 steps were examined to describe the rates of formation of the observed products and reaction intermediates for hydrogenation of HAH over Ru and Pd catalysts, and a 3-step scheme was studied over Cu catalysts. Rate constants and activation energies were calculated using these reaction schemes, and we then apply these reaction schemes to explore the effects of water addition on the hydrogenation pathways. The effects of water addition to isopropanol (IPA) solvents on the hydrogenation of HAH were markedly different over Pd, Ru, and Cu catalysts. Over the Pd catalyst, the addition of water to IPA increased hydrogenation rates and promoted hydrogenation of furan rings. The addition of water to IPA yielded significant carbon losses over the Ru catalyst, and slowed hydrogenation steps over Cu, while significantly inhibiting hydrogenation of the ketone group. This behavior opened routes toward increased production rates of PHAH=O (a partially hydrogenated form of HAH containing a C=O bond), a product in which the diene groups of the furan rings were not hydrogenated. Addition of water also allowed increased feed concentrations of HAH that were previously not possible in pure IPA solvents.

09 BIOMASS FUELS↗

A Multiport DC Transformer to Enable Flexible Scalable DC as a Service

The rapid adoption of new DC loads and sources, including photovoltaic arrays, DC fast charging of electric vehicle, battery energy storage and data centers, requires a large amount of DC power conversion. A majority of new deployments also necessitate the integration of multiple DC loads and sources at one site. The traditional approach to serve these new applications relies on multiple standard power converters, each dedicated to a source or load, and results in highly customized systems, with challenging control coordination, complex protection strategies, and poor scalability. Instead, this paper proposes the concept of a multiport DC transformer (MDCT) as a modular building block for realizing a flexible, scalable DC as a Service system and address this rapidly growing need. The MDCT uses the S4T to achieve very tight control of cycle-by-cycle energy exchange between multiple ports, with high efficiency. A single multiport converter replaces 4-6 distinct converters, integrates all energy flows and manages protection. As a result, a new layered control architecture is introduced to ensure stability and scalability of the MDCT, with multiple S4T power converter building blocks connected in parallel to realize a fully modular system and reach the target power levels.

30 DIRECT ENERGY CONVERSION↗

Ion and Electron Acoustic Bursts during Anti-Parallel Reconnection Driven by Lasers

Magnetic reconnection converts magnetic energy into thermal and kinetic energy in plasma. Among the numerous candidate mechanisms, ion acoustic instabilities driven by the relative drift between ions and electrons (or equivalently, electric current) have been suggested to play a critical role in dissipating magnetic energy in collisionless plasmas. However, their existence and effectiveness during reconnection have not been well understood due to ion Landau damping and difficulties in resolving the Debye length scale in the laboratory. We report a sudden onset of ion acoustic bursts measured by collective Thomson scattering in the exhaust of anti-parallel magnetically driven reconnection using high-power lasers. The ion acoustic bursts are followed by electron acoustic bursts with electron heating and bulk acceleration. We reproduce these observations with one- and two-dimensional particle-in-cell simulations in which an electron outflow jet drives ion acoustic instabilities, forming double layers. These layers induce electron two-stream instabilities that generate electron acoustic bursts and energize electrons. Our results demonstrate the importance of ion and electron acoustic dynamics during reconnection when ion Landau damping is ineffective, a condition applicable to a range of astrophysical plasmas including near-Earth space, stellar flares and black hole accretion engines.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Stacked Low-Inertia Converter or Solid-State Transformer: Modeling and Model Predictive Priority-Shifting Control for Voltage Balance

This paper presents control challenges of stacked low-inertia converter (SLIC) or cascaded reduced dc-link solid-state transformer (SST) and proposes a novel model predictive priority-shifting (MPPS) control with implicit modulator and a discrete-time large-signal model for voltage balancing and dc-link regulation. Low-inertia converters, featuring small electrolytic capacitor-less dc links, dramatically reduce cost, size, and weight compared to conventional solutions. However, without a large dc-link buffer, the input and output are tightly coupled, leading to significant control challenges. The control becomes even more challenging with these converters stacked input-series output-parallel (ISOP) for medium-voltage (MV) grid, which causes coupling between the modules besides the coupling within each module. This paper analyzes the multi-objective, multi-degree of freedom control problem, using the modular soft-switching solid-state transformer (M-S4T) as an example of the SLIC. First, distribution of control efforts under controller saturation is critical because multiple control objectives can be conflicting, especially when the module voltages are unbalanced and are being restored. The MPPS can shift the priorities to address this issue. Second, due to the low inertia and high dc-link ripple, classic space vector pulse-width modulation (SVPWM), average model with small-ripple assumption, and control design based on small-signal model cannot accurately modulate, model, and control the nonlinear reduced dc link. Therefore, a discrete-time large-signal model of the M-S4T is established to derive the predictive control in the MPPS. The MPPS and the PI control are compared in MV simulations to show the issue of applying the PI to the SLIC and the effectiveness of the MPPS for voltage balancing and dc-link regulation in a deadbeat manner. Finally, the proposed control is tested on a 5 kV ISOP SiC SST prototype to verify priority shifting to address controller saturation issue and fast and robust voltage balancing.

14 SOLAR ENERGY↗

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.↗

High-Efficiency Hall Thruster Discharge Power Converter

Busek Company, Inc., is designing, building, and testing a new printed circuit board converter. The new converter consists of two series or parallel boards (slices) intended to power a high-voltage Hall accelerator (HiVHAC) thruster or other similarly sized electric propulsion devices. The converter accepts 80- to 160-V input and generates 200- to 700-V isolated output while delivering continually adjustable 300-W to 3.5-kW power. Busek built and demonstrated one board that achieved nearly 94 percent efficiency the first time it was turned on, with projected efficiency exceeding 97 percent following timing software optimization. The board has a projected specific mass of 1.2 kg/kW, achieved through high-frequency switching. In Phase II, Busek optimized to exceed 97 percent efficiency and built a second prototype in a form factor more appropriate for flight. This converter then was integrated with a set of upgraded existing boards for powering magnets and the cathode. The program culminated with integrating the entire power processing unit and testing it on a Busek thruster and on NASA's HiVHAC thruster.

Jaquish, Thomas↗

PARAMESH: A Parallel Adaptive Mesh Refinement Community Toolkit

In this paper, we describe a community toolkit which is designed to provide parallel support with adaptive mesh capability for a large and important class of computational models, those using structured, logically cartesian meshes. The package of Fortran 90 subroutines, called PARAMESH, is designed to provide an application developer with an easy route to extend an existing serial code which uses a logically cartesian structured mesh into a parallel code with adaptive mesh refinement. Alternatively, in its simplest use, and with minimal effort, it can operate as a domain decomposition tool for users who want to parallelize their serial codes, but who do not wish to use adaptivity. The package can provide them with an incremental evolutionary path for their code, converting it first to uniformly refined parallel code, and then later if they so desire, adding adaptivity.

MacNeice, Peter↗

Coarrars for Parallel Processing

The design of the Coarray feature of Fortran 2008 was guided by answering the question "What is the smallest change required to convert Fortran to a robust and efficient parallel language." Two fundamental issues that any parallel programming model must address are work distribution and data distribution. In order to coordinate work distribution and data distribution, methods for communication and synchronization must be provided. Although originally designed for Fortran, the Coarray paradigm has stimulated development in other languages. X10, Chapel, UPC, Titanium, and class libraries being developed for C++ have the same conceptual framework.

Fortran↗

GPS on-orbit battery performance

Three batteries designed for the GPS system were evaluated. The batteries were wired together, and during the eclipse period were discharged through parallel diodes into a boost converter which then boosted the battery voltage up to the totally regulated bus voltage. Each battery, with a system life of approximately five years, had its own charger. During testing the battery was maintained or used on trickle charge. Data are presented for the battery capacity during the reconditioning. Raw data for each eclipse period and calculations for the average discharge voltage for each battery are given. Thermal cycling for one of the batteries and reconditioning cycles and regimes for all of the batteries are discussed. A reconditioning discharge curve is also given. The problem of temperature cycling in one of the batteries was resolved by redesigning the battery radiator system.

Kasten, J. L.↗

Optical control of an 8-element Ka-band phased array using a high-speed optoelectronic interconnect

Optical distribution of control signals in electronically steered phased array antennas is being considered. A demonstration experiment is described in which a high speed hybrid GaAs optoelectronic integrated circuit (OEIC) was used to control an eight element phased array antenna. The OEIC, which accepts a serial optical control signal as input and converts it to 16 demultiplexed parallel outputs, was used to control the monolithic GaAs phase shifters of a Ka-band patch panel array antenna. Antenna pattern switching speeds of 2.25 microsec, limited by interface circuitry, were observed.

Richard, M. A.↗

Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

Zhou, Zhimin↗

Credit based flow control mechanism for use in multiple link width interconnect systems

Flow control credit management is provided when converting traffic from a first parallel link width on a first link to a second parallel link width on a second link A current value is calculated for a variable flow control credit exchange rate (R) associated with the first and second links. A first flow control credit indicator is received on the second link, and a credit amount calculated based on the first flow control credit indicator and R. A second flow control credit indicator for the credit amount is then transmitted on the first link.

42 ENGINEERING↗

System and method of storing and analyzing information

A system and method of storing and analyzing information is disclosed. The system includes a compiler layer to convert user queries to data parallel executable code. The system further includes a library of multithreaded algorithms, processes, and data structures. The system also includes a multithreaded runtime library for implementing compiled code at runtime. The executable code is dynamically loaded on computing elements and contains calls to the library of multithreaded algorithms, processes, and data structures and the multithreaded runtime library.

Feo, John T.↗