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NASA NTRS1992

A new fabrication technique for back-to-back varactor diodes

A new varactor diode process has been developed in which much of the processing is done from the back of an extremely thin semiconductor wafer laminated to a low-dielectric substrate. Back-to-back BNN diodes were fabricated with this technique; excellent DC and low-frequency capacitance measurements were obtained. Advantages of the new technique relative to other techniques include greatly reduced frontside wafer damage from exposure to process chemicals, improved capability to integrate devices (e.g. for antenna patterns, transmission lines, or wafer-scale grids), and higher line yield. BNN diodes fabricated with this technique exhibit approximately the expected capacitance-voltage characteristics while showing leakage currents under 10 mA at voltages three times that needed to deplete the varactor. This leakage is many orders of magnitude better than comparable Schottky diodes.

Smith, R. Peter↗

NASA NTRS1972

Design, performance, and evaluation of a direct-current contactor for space nuclear electrical systems

A direct-current contactor for use in large space power systems was designed, built, and tested. It was developed to be operational in an environment of 540 C and at a pressure of 0.0001 N/sq m or lower. The contactor is rated to pass 10 A continuously and to interrupt a 20-A current at 10,000 V. It was tested to determine the corona threshold level and the leakage current at different temperatures. Also, it was tested for its closing and interruption ability.

Mueller, L. A.↗

NASA NTRS1989

Mechanism for nearly ohmic behavior in annealed Au/n-GaAs Schottky diodes

The mechanism of the ohmic behavior commonly observed after annealing Au/n-GaAs 110-oriented Schottky diodes was investigated using electron-beam-induced current (EBIC) measurements, secondary electron imaging (SEI), and SEM and TEM observations. The results showed that the ohmic behavior of annealed Schottky diodes originates from a shunt current pathway at the diode periphery. The SEI, EBIC, and electrical measurements indicated that the ohmic leakage current is due to the surface recombinations at the exposed surface of GaAs between elongated Au crystallites.

Leon, R. P.↗

NASA NTRS2001

2D Quantum Transport Modeling in Nanoscale MOSFETs

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Svizhenko, Alexei↗

NASA NTRS1989

Induced emission of radiation from a large space-station-like structure in the ionosphere

Large conducting structures in the ionosphere may have currents flowing through them which close in the ionospheric plasma. These currents can arise either from current leakage from an onboard power distribution system or by being induced by the motional electric field. Associated with these currents will be broadband electromagnetic radiation in the Alfven and lower hybrid bands. The radiation impedance of this electromagnetic radiation is explored for a structure of space-station-like dimensions as a function of the geometry of the structure and the composition of the ionic environment. It is shown that modification of the collecting area of the structure and environment can be used to minimize the radiation impedance. For a space station, the radiated power will at most be of the order of watts, which does not represent a significant power loss. However, the radiation field will give rise to a substantial pollution of the electromagnetic spectrum in the vicinity of the space station. Design choices to minimize this interference are suggested.

Hastings, D. E.↗

NASA NTRS2008

Characterization of Piezoelectric Stacks for Space Applications

Future NASA missions are increasingly seeking to actuate mechanisms to precision levels in the nanometer range and below. Co-fired multilayer piezoelectric stacks offer the required actuation precision that is needed for such mechanisms. To obtain performance statistics and determine reliability for extended use, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and high temperatures and voltages. In order to study the lifetime performance of these stacks, five actuators were driven sinusoidally for up to ten billion cycles. An automated data acquisition system was developed and implemented to monitor each stack's electrical current and voltage waveforms over the life of the test. As part of the monitoring tests, the displacement, impedance, capacitance and leakage current were measured to assess the operation degradation. This paper presents some of the results of this effort.

active mirrors↗

NASA NTRS1983

Leakage effects in n-GaAs MESFET with n-GaAs buffer layer

Whereas improvement of the interface between the active layer and the buffer layer has been demonstrated, the leakage effects can be important if the buffer layer resistivity is not sufficiently high and/or the buffer layer thickness is not sufficiently small. It was found that two buffer leakage currents exist from the channel under the gate to the source and from drain to the channel in addition to the buffer leakage resistance between drain and source. It is shown that for a 1 micron gate-length n-GaAs MESFET, if the buffer layer resistivity is 12 OHM-CM and the buffer layer thickness h is 2 microns, the performance of the device degrades drastically. It is suggested that h should be below 2 microns.

Wang, Y. C.↗

NASA NTRS2006

Low Temperature (30 K) TID Test Results of a Radiation Hardened 128 Channel Serial-to-Parallel Converter

This viewgraph presentation reviews the low temperature, Total Ionizing Dose (TID) tests of radiation hardened serial to parallel converter to be used on the James Webb Space Telescope. The test results show that the original HV583 level shifter - a COTS part -was not suitable for JWST because the supply currents exceeded specs after 20 krad( Si) .The HV584 - functionally similar to the HV583 -was designed using RHBD approach that reduced the leakage currents to within acceptable levels and had only a small effect on the level-shifted output voltage.

Meyer, Stephen↗

NASA NTRS2009

Lightning Pin Injection Testing on MOSFETS

Lightning transients were pin-injected into metal-oxide-semiconductor field-effect transistors (MOSFETs) to induce fault modes. This report documents the test process and results, and provides a basis for subsequent lightning tests. MOSFETs may be present in DC-DC power supplies and electromechanical actuator circuits that may be used on board aircraft. Results show that unprotected MOSFET Gates are susceptible to failure, even when installed in systems in well-shielded and partial-shielded locations. MOSFET Drains and Sources are significantly less susceptible. Device impedance decreased (current increased) after every failure. Such a failure mode may lead to cascading failures, as the damaged MOSFET may allow excessive current to flow through other circuitry. Preliminary assessments on a MOSFET subjected to 20-stroke pin-injection testing demonstrate that Breakdown Voltage, Leakage Current and Threshold Voltage characteristics show damage, while the device continues to meet manufacturer performance specifications. The purpose of this research is to develop validated tools, technologies, and techniques for automated detection, diagnosis and prognosis that enable mitigation of adverse events during flight, such as from lightning transients; and to understand the interplay between lightning-induced surges and aging (i.e. humidity, vibration thermal stress, etc.) on component degradation.

Ely, Jay J.↗

NASA NTRS2016

Solar Array at Very High Temperatures: Ground Tests

Solar array design for any spacecraft is determined by the orbit parameters. For example, operational voltage for spacecraft in Low Earth Orbit (LEO) is limited by significant differential charging due to interactions with low temperature plasma. In order to avoid arcing in LEO, solar array is designed to generate electrical power at comparatively low voltages (below 100 V) or to operate at higher voltages with encapsulated of all suspected discharge locations. In Geosynchronous Orbit (GEO) differential charging is caused by energetic electrons that produce differential potential between coverglass and conductive spacecraft body in a kilovolt range. In such a case, weakly conductive layer over coverglass (ITO) is one of possible measures to eliminate dangerous discharges on array surface. Temperature variations for solar arrays in both orbits are measured and documented within the range of -150 C +110 C. This wide interval of operational temperatures is regularly reproduced in ground tests with radiative heating and cooling inside shroud with flowing liquid nitrogen. The requirements to solar array design and tests turn out to be more complicated when planned trajectory crosses these two orbits and goes closer to Sun. Conductive layer over coverglass causes sharp increase in parasitic current collected from LEO plasma, high temperature may cause cracks in encapsulating material (RTV), radiative heating of coupon in vacuum chamber becomes practically impossible above 150 C, conductivities of glass and adhesive go up with temperature that decrease array efficiency, and mechanical stresses grow up to critical magnitudes. A few test arrangements and respective results are presented in current paper. Coupons were tested against arcing in simulated LEO and GEO environments under elevated temperatures up to 200 C. The dependence of leakage current on temperature was measured, and electrostatic cleanness was verified for coupons with antireflection (AR) coating over ITO layer.

differential charging↗

NASA NTRS2016

Solar Array at Very High Temperatures: Ground Tests

Solar array design for any spacecraft is determined by the orbit parameters. For example, operational voltage for spacecraft in Low Earth Orbit (LEO) is limited by significant differential charging due to interactions with low temperature plasma. In order to avoid arcing in LEO, solar array is designed to generate electrical power at comparatively low voltages (below 100 volts) or to operate at higher voltages with encapsulation of all suspected discharge locations. In Geosynchronous Orbit (GEO) differential charging is caused by energetic electrons that produce differential potential between the coverglass and the conductive spacecraft body in a kilovolt range. In such a case, the weakly conductive layer over coverglass, indium tin oxide (ITO) is one of the possible measures to eliminate dangerous discharges on array surface. Temperature variations for solar arrays in both orbits are measured and documented within the range of minus150 degrees Centigrade to plus 1100 degrees Centigrade. This wide interval of operational temperatures is regularly reproduced in ground tests with radiative heating and cooling inside a shroud with flowing liquid nitrogen. The requirements to solar array design and tests turn out to be more complicated when planned trajectory crosses these two orbits and goes closer to the Sun. The conductive layer over coverglass causes a sharp increase in parasitic current collected from LEO plasma, high temperature may cause cracks in encapsulating (Room Temperature Vulcanizing (RTV) material; radiative heating of a coupon in vacuum chamber becomes practically impossible above 1500 degrees Centigrade; conductivities of glass and adhesive go up with temperature that decrease array efficiency; and mechanical stresses grow up to critical magnitudes. A few test arrangements and respective results are presented in current paper. Coupons were tested against arcing in simulated LEO and GEO environments under elevated temperatures up to 2000 degrees Centigrade. The dependence of leakage current on temperature was measured, and electrostatic cleanness was verified for coupons with antireflection (AR) coating over the indium tin oxide (ITO) layer.

differential charging↗

NASA NTRS1990

Interactions between the Space Station and the environment: A preliminary assessment of EMI

A review of the interactions between proposed Space Station systems/payloads and the environment that contribute to electromagnetic interference was performed. Seven prime sources of interference have been identified. These are: The Space Station power system; active experiments such as beam injection; ASTROMAG; ram and wake density gradients; pick up ions produced by vented or offgassed clouds; waves produced by current loops that include the plasma and structure; arcing from high voltage solar arrays (or possible ESD in polar orbit). This review indicates that: minimizing leakage current from the 20 kHz power system to the structure; keeping the surfaces of the Space Station structure, arrays, and radiators nonconducting; minimizing venting of payloads or systems to non-operational periods; careful placement of payloads sensitive to magnetic field perturbations or wake noise; and designing an operational timeline compatible with experiment requirement are the most effective means of minimizing the effects of this interference. High degrees of uncertainty exist in the estimates of magnitudes of gas emission induced EMI, radiation of 20 kHz and harmonics, ASTROMAG induced interference, and arc threshold/frequency of the solar array. These processes demand further attention so that mitigation efforts are properly calibrated.

Murphy, G. B.↗

NASA NTRS1997

Investigation of Field Emitter Array Vacuum Microtriodes for Space Electronics Applications

Research into processing techniques for fabrication of vacuum microelectronic devices has been carried out, with special emphasis being given to the growth of silicon dioxide thin films. Oxide films ranging from 30 nm to approximately 2 micrometers have been grown on single crystal silicon wafers. Metal-oxide-semiconductor capacitor test structures have been made from some of these oxide films, and current-versus-voltage plots for these structures have been measured. It has been observed that the rate of applied voltage across the oxide films produces marked differences in measured leakage current. Breakdown fields across two of the thinnest oxide films have been measured and are comparable with highest values reported in literature. Several silicon wafers were processed to make field- emitter array diodes, and were delivered to collaborators at NASA-Lewis Research Center for final fabrication steps and testing.

Smith, Mark A.↗

NASA NTRS1992

InGaAs/InGaAsP/InP strained-layer quantum well lasers at about 2 microns

The first successful operation of InGaAs strained layer quantum well (Sl-QW) injection lasers at about 2 microns is reported. The threshold current density and the external differential quantum efficiency of 5 microns wide and 800 microns long ridge waveguide lasers were 2.5 kA/sq cm and 6 percent, respectively. The devices had a reverse leakage current of less than 20 micro-A at -1 V indicating epitaxial layers with low defect density.

Forouhar, S.↗

NASA NTRS1992

Room-temperature operation of MOCVD-grown GaInAs/InP strained-layer multiquantum well lasers in 1.8 micron range

The first successful room-temperature pulsed operation is reported of InGaAs strained layer multiquantum well injection lasers grown by MOVPE on InP substrates in the 1.8 micron range. The threshold current density and the external differential quantum efficiency of the 10 micron wide ridge waveguide lasers were 2.5 kA/sq cm (cavity length = 1 mm) and 5 percent (cavity length = 400 microns), respectively. Broad-area lasers, 100 microns wide and 1 mm long, had a reverse leakage current of less than 10 microamps at -1 V indicating high quality of the epitaxial layers.

Forouhar, S.↗

NASA NTRS1998

Breakdown Degradation Associated with Elementary Screw Dislocations in 4H-SiC P(+)N Junction Rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector greater than 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = lc with no hollow core) in densities on the order of thousands per sq cm, nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current-voltage (I-V) characteristics of 4H-SiC p(+)n diodes. First, Synchrotron White Beam X-ray Topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p(+)n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I-V knee, and no visible concentration of breakdown current. In contrast devices that contained at least one elementary screw dislocation exhibited a 5% to 35% reduction in breakdown voltage, a softer breakdown I-V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.

Neudeck, P. G.↗

NASA NTRS1987

Advanced Components for Spaceborne Infrared Astronomy

Basic improvements in the technology of low noise read-out systems for low background detectors were demonstrated. Using discrete JFET integrating amplifiers at their optimum temperature of 55 K, read noise less than 7.5 electrons in 128 seconds of integration was obtained. Two models of single channel integrators are now available, the JF-77 for use between 50 and 80 K and the JF-4 for lower temperatures. A 1 x 15 linear array of complete integrators on a single integrated circuit was developed and will be made available in the near future. The successful operation of a superconducting stepper motor was demonstrated. The motor shows a three fold increase in torque over conventional motors operating at room temperature. The success of the motor stems from the use of superconducting coils in conjunction with developments in bearings for cryogenic use, rare-earth rotors, and motor cooling techniques. The current state of development will allow the rapid development of motors optimized for specific applications. An electronic switch capable of resetting cooled JFET integrating amplifiers was developed. The JFET integrating amplifiers that use this switch have demonstrated read noise of less than 10 electrons. The JFET reset device exhibits an extremely high open impedance and low leakage current. Capacitance is sufficiently low so as not to impair amplifier sensitivity. The effects of transient switching charges are minimized by a compensation technique and variable transient current problems inherent to devices of this type are overcome by external circuity.

Davidson, Arnold W.↗

NASA NTRS1998

Numerical Examination of Silicon Avalanche Photodiodes Operated in Charge Storage Mode

The behavior of silicon-based avalanche photodiodes (APD's) operated in the charge storage mode is examined. In the charge storage mode, the diodes are periodically biased to a sub-breakdown voltage and then open-circuited. During this integration period, photo-excited and thermally generated carriers are accumulated within the structure. The dynamics of this accumulation and its effects upon the avalanching of the diode warrants a detailed, fully numerical analysis. The salient features of this investigation include device sensitivity to the input photo-current including the self-quenching effect of the diode and its limitations in sensing low light levels, the dependence of the response on the bulk lifetime and hence on the generation current within the device, the initial gain, transient response, dependence of the device uniformity upon performance, and the quantity of storable charge within the device. To achieve these tasks our device simulator, STEBS-2D, was utilized. A modified current-controlled boundary condition is employed which allows for the simulation of the isolated diode after the initial reset bias has been applied. With this boundary condition, it is possible to establish a steady-state voltage on the ohmic contact and then effectively remove the device from the external circuit while still including effects from surface recombination, trapped surface charge, and leakage current from the read-out electronics.

Parks, Joseph W., Jr.↗