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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

High-gain AlGaAs/GaAs double heterojunction Darlington phototransistors for optical neural networks

High-gain MOCVD-grown (metal-organic chemical vapor deposition) AlGaAs/GaAs/AlGaAs n-p-n double heterojunction bipolar transistors (DHBTs) and Darlington phototransistor pairs are provided for use in optical neural networks and other optoelectronic integrated circuit applications. The reduced base doping level used results in effective blockage of Zn out-diffusion, enabling a current gain of 500, higher than most previously reported values for Zn-diffused-base DHBTs. Darlington phototransitor pairs of this material can achieve a current gain of over 6000, which satisfies the gain requirement for optical neural network designs, which advantageously may employ neurons comprising the Darlington phototransistor pairs in series with a light source.

Kim, Jae H.↗
NASA NTRS1992

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.

Cunningham, Thomas J.↗
NASA NTRS1992

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

Cunningham, Thomas J.↗
NASA NTRS1993

Complementary heterojunction FET technology for space application

A 32-bit serial integer multiplier was designed to investigate the yield and performance of complementary heterojunction FET (CHFET) technology. This is the largest reported CHFET logic circuit. The maximum operating frequency was 500 MHz. Very low power dissipation of 3 mW was obtained at 5 MHz operation. Single-event upset (SEU) characteristics of CHFET devices and latches were also measured and indicates the potential for SEU hard circuits for space and military applications.

Larue, George↗
NASA NTRS1992

Heterojunction bipolar transistor technology for data acquisition and communication

Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.

Wang, C.↗
NASA NTRS1994

Epitaxial heterojunctions of oxide semiconductors and metals on high temperature superconductors

Epitaxial heterojunctions formed between high temperature superconductors and metallic or semiconducting oxide barrier layers are provided. Metallic perovskites such as LaTiO3, CaVO3, and SrVO3 are grown on electron-type high temperature superconductors such as Nd(1.85)Ce(0.15)CuO(4-x). Alternatively, transition metal bronzes of the form A(x)MO(3) are epitaxially grown on electron-type high temperature superconductors. Also, semiconducting oxides of perovskite-related crystal structures such as WO3 are grown on either hole-type or electron-type high temperature superconductors.

Vasquez, Richard P.↗
NASA NTRS1999

Copper-Based OHMIC Contracts for the Si/SiGe Heterojunction Bipolar Transistor Structure

Silicon based heterojunction bipolar transistors (HBT) with SiGe base are potentially important devices for high-speed and high-frequency microelectronics. These devices are particularly attractive as they can be fabricated using standard Si processing technology. However, in order to realize the full potential of devices fabricated in this material system, it is essential to be able to form low resistance ohmic contacts using low thermal budget process steps and have full compatibility with VLSI/ULSI processing. Therefore, a study was conducted in order to better understand the contact formation and to develop optimized low resistance contacts to layers with doping densities corresponding to the p-type SiGe base and n-type Si emitter regions of the HBTS. These as-grown doped layers were implanted with BF(sub 2) up to 1 X 10(exp 16)/CM(exp 2) and As up to 5 x 10(exp 15)/CM2, both at 30 keV for the p-type SiGe base and n-type Si emitter layers, respectively, in order to produce a low sheet resistance surface layer. Standard transfer length method (TLM) contact pads on both p and n type layers were deposited using an e-beam evaporated trilayer structure of Ti/CufTi/Al (25)A/1500A/250A/1000A). The TLM pads were delineated by a photoresist lift-off procedure. These contacts in the as-deposited state were ohmic, with specific contact resistances for the highest implant doses of the order of 10(exp -7) ohm-CM2 and lower.

Das, Kalyan↗
NASA NTRS2003

Long-Term Reliability of High Speed SiGe/Si Heterojunction Bipolar Transistors

Accelerated lifetime tests were performed on double-mesa structure Si/Si0.7Ge0.3/Si npn heterojunction bipolar transistors, grown by molecular beam epitaxy, in the temperature range of 175C-275C. Both single- and multiple finger transistors were tested. The single-finger transistors (with 5x20 micron sq m emitter area) have DC current gains approximately 40-50 and f(sub T) and f(sub MAX) of up to 22 GHz and 25 GHz, respectively. The multiple finger transistors (1.4 micron finger width, 9 emitter fingers with total emitter area of 403 micron sq m) have similar DC current gain but f(sub T) of 50 GHz. It is found that a gradual degradation in these devices is caused by the recombination enhanced impurity diffusion (REID) of boron atoms from the p-type base region and the associated formation of parasitic energy barriers to electron transport from the emitter to collector layers. This REID has been quantitatively modeled and explained, to the first order of approximation, and the agreement with the measured data is good. The mean time to failure (MTTF) of the devices at room temperature is estimated from the extrapolation of the Arrhenius plots of device lifetime versus reciprocal temperature. The results of the reliability tests offer valuable feedback for SiGe heterostructure design in order to improve the long-term reliability of the devices and circuits made with them. Hot electron induced degradation of the base-emitter junction was also observed during the accelerated lifetime testing. In order to improve the HBT reliability endangered by the hot electrons, deuterium sintered techniques have been proposed. The preliminary results from this study show that a deuterium-sintered HBT is, indeed, more resistant to hot-electron induced base-emitter junction degradation. SiGe/Si based amplifier circuits were also subjected to lifetime testing and we extrapolate MTTF is approximately 1.1_10(exp 6) hours at 125iC junction temperature from the circuit lifetime data.

Ponchak, George E.↗
NASA NTRS1993

Photoresponse Model for Si_(1-x)Ge_x/Si Heterojunction Internal Photoemission Infrared Detector

A photoresponse model has been developed for the Si_(1-x)Ge_x/Si heterojunction internalphotoemission (HIP) infrared detector at wavelengths corresponding to photon energies less than theFermi energy. A Si_(0.7)Ge_(0.3)/Si HIP detector with a cutoff wavelength of 23 micrometers andan emission coefficient of 0.4 eV^(-1) has been demonstrated. The model agrees with the measureddetector response at lambda greater than 8 micrometers. The potential barrier determined by themodel is in close agreement (difference similar to 4 meV) with the potential barrier determined by theRichardson plot, compared to the discrepancies of 20-50 meV usually observed for PtSi Schottkydetectors.

Lin, T.↗
NASA NTRS1979

Heterojunction semiconductor device

A layer of germanium on a body of P type conductivity single crystal indium phosphide provides a blocking heterojunction. This device will emit light when a suitable voltage is placed thereacross or the device can be used as a photoconductor to generate electrons when light is directed thereon.

Harwylo, Frank Z.↗
NASA NTRS2009

InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

Radisic, Vesna↗
NASA NTRS2010

InGaP Heterojunction Barrier Solar Cells

A new solar-cell structure utilizes a single, ultra-wide well of either gallium arsenide (GaAs) or indium-gallium-phosphide (InGaP) in the depletion region of a wide bandgap matrix, instead of the usual multiple quantum well layers. These InGaP barrier layers are effective at reducing diode dark current, and photogenerated carrier escape is maximized by the proper design of the electric field and barrier profile. With the new material, open-circuit voltage enhancements of 40 and 100 mV (versus PIN control systems) are possible without any degradation in short-circuit current. Basic tenets of quantum-well and quantum- dot solar cells are utilized, but instead of using multiple thin layers, a single wide well works better. InGaP is used as a barrier material, which increases open current, while simultaneously lowering dark current, reducing both hole diffusion from the base, and space charge recombination within the depletion region. Both the built-in field and the barrier profile are tailored to enhance thermionic emissions, which maximizes the photocurrent at forward bias, with a demonstrated voltage increase. An InGaP heterojunction barrier solar cell consists of a single, ultra-wide GaAs, aluminum-gallium-arsenide (AlGaAs), or lower-energy-gap InGaP absorber well placed within the depletion region of an otherwise wide bandgap PIN diode. Photogenerated electron collection is unencumbered in this structure. InGaAs wells can be added to the thick GaAs absorber layer to capture lower-energy photons.

Welser, Roger E.↗
NASA NTRS2014

InGaP Heterojunction Barrier Solar Cells

A new solar cell structure called a heterojunction barrier solar cell is described. As with previously reported quantum-well and quantum-dot solar cell structures, a layer of narrow band-gap material, such as GaAs or indium-rich InGaP, is inserted into the depletion region of a wide band-gap PN junction. Rather than being thin, however, the layer of narrow band-gap material is about 400-430 nm wide and forms a single, ultrawide well in the depletion region. Thin (e.g., 20-50 nm), wide band-gap InGaP barrier layers in the depletion region reduce the diode dark current. Engineering the electric field and barrier profile of the absorber layer, barrier layer, and p-type layer of the PN junction maximizes photogenerated carrier escape. This new twist on nanostructured solar cell design allows the separate optimization of current and voltage to maximize conversion efficiency.

Welser, Roger E.↗