Spacecraft telecommunications systems - A digital command system development
All digital, single channel command subsystem for spacecraft communication
Tegnelia, C. R.↗
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Fermilab PIP II Machine Protection System Digitized Data Noise Elimination Scheme and Its FPGA Implementation
In Fermilab's PIP-II machine protection system, beam loss signals from various detectors are digitized at 125 MS/s. Noise from both high-frequency sources and low-frequency 60 Hz AC power equipment can con-taminate the data. To suppress noise across these ranges especially 60 Hz and its harmonics, which overlap with beam loss signal frequencies advanced digital processing beyond standard filtering is re-quired. Several real-time functional blocks were simu-lated and tested on an FPGA: (1) a dual time-constant discharging integrator filter, (2) a de-ripple baseline extraction and storage block, and (3) a fast-recovery discharging integrator. The nonlinear IIR integrator filter removes high-frequency noise and feeds into the baseline extractor. Upon detecting abrupt beam loss, it switches to a longer time constant to prevent baseline distortion. The de-ripple block calculates a valid base-line by averaging over multiple 60 Hz periods, storing results in a 4096-word FPGA RAM. This baseline is subtracted from raw data before integration by the fast-recovery block, which resets quickly after use. All blocks achieved expected performance.
Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗
Fermilab PIP II machine protection system digitized data noise elimination scheme and its FPGA implementation
In Fermilab's PIP-II machine protection system, beam loss signals from various detectors are digitized at 125 MS/s. Noise from both high-frequency sources and low-frequency 60 Hz AC power equipment can contaminate the data. To suppress noise across these ranges especially 60 Hz and its harmonics, which overlap with beam loss signal frequencies advanced digital processing beyond standard filtering is required. Several real-time functional blocks were simulated and tested on an FPGA: (1) a dual time-constant discharging integrator filter, (2) a de-ripple baseline extraction and storage block, and (3) a fast-recovery discharging integrator. The nonlinear IIR integrator filter removes high-frequency noise and feeds into the baseline extractor. Upon detecting abrupt beam loss, it switches to a longer time constant to prevent baseline distortion. The de-ripple block calculates a valid baseline by averaging over multiple 60 Hz periods, storing results in a 4096-word FPGA RAM. This baseline is subtracted from raw data before integration by the fast-recovery block, which resets quickly after use. All blocks achieved expected performance.
Wu, J. [Fermilab] (ORCID:0000000344329521)↗
Codes and coding circuitry for automatic error correction within digital systems technical report no. 2
Codes and coding circuits for automatic error correction in digital computers
CODE↗
Arithmetic error codes - Cost and effectiveness studies for application in digital system design.
The application of error-detecting or error-correcting codes in digital computer design requires studies of cost and effectiveness tradeoffs to supplement the knowledge of their theoretical properties. General criteria for cost and effectiveness studies of error codes are developed, and results are presented for arithmetic error codes with the low-cost check modulus 2 super a - 1. Both separate (residue) and nonseparate (AN) codes are considered. The class of multiple arithmetic error codes is developed as an extension of low-cost single codes.
Avizienis, A.↗
Digital system for dynamic turbine engine blade displacement measurements
An instrumentation concept for measuring blade tip displacements which employs optical probes and an array of micro-computers is presented. The system represents a hitherto unknown instrumentation capability for the acquisition and direct digitization of deflection data concurrently from all of the blade tips of an operational engine rotor undergoing flutter or forced vibration. System measurements are made using optical transducers which are fixed to the case. Measurements made in this way are the equivalent of those obtained by placing three surface-normal displacement transducers at three positions on each blade of an operational rotor.
Kiraly, L. J.↗
Earth System Digital Twins (ESDT)
"First Webinar for a digital twin webinar series titled ""Digital Twin Webinar Series 1: Concept, Practices, and Vision"". This kick-off webinar will focus on concepts, architecture and high level discussion on digital twins for Earth science and other domain sciences. The agenda will be the following: - Dr. Jacqueline Le Moigne is NASA AIST program manager, and the first federal program manager to programmatically fund 14 digital twin research projects. - Mr. Stan Posey is the HPC Program Manager, ESM and CFD Domains at NVIDIA. - Dr. Goodchild is a emeritus professor at UCSB, member of the national academy, and a founder of digital earth international society."
Information Systems↗
The SIR-C ground data system: Digital processor, data products, information flow
The SIR-C (Shuttle Imaging Radar) instrument will collect both C-Band and L-Band data with each frequency band consisting of direct (HH or VV) and cross-polarized (HV or VH) data. Considering all possible combinations as many as eight different data channels will be available for any given target area. This data will be digitized and formatted on-board for direct downlink via the Tracking and Data Relay Satellite System (TDRSS), or it will be buffered through on-board high density digital recorders for storage or transmission when TDRSS is available. The data is received by the TDRSS ground station at White Sands and is nominally relayed via DOMSAT to the high data rate recording facility at GSFC. The tapes are then shipped to JPL for processing into imagery and eventual distribution to the SIR-C investigators.
Curlander, John C.↗
On reliability modeling and analysis of ultrareliable fault-tolerant digital systems.
The processes of protective redundancy, namely, standby replacement (SR) redundancy and hybrid redundancy (a combination of SR and multiple-line voting redundancy), find application in the architecture of fault-tolerant digital computers and enable them to be ultrareliable and self-repairing. The claims to ultrareliability lead to the challenge of quantitatively evaluating and assigning a value to the probability of survival as a function of the mission durations intended. This note presents various mathematical models, and derives and displays quantitative evaluations of system reliability as a function of various mission parameters of interest to the system designer.
Mathur, F. P.↗
Power switching trims digital system weight, cost.
Series power switch for orientation and position computer of small lunar-orbit spacecraft designed to reduce weight and cost
POWER-LIMITED VEHICLE↗
Multichannel Brain-Signal-Amplifying and Digitizing System
An apparatus has been developed for use in acquiring multichannel electroencephalographic (EEG) data from a human subject. EEG apparatuses with many channels in use heretofore have been too heavy and bulky to be worn, and have been limited in dynamic range to no more than 18 bits. The present apparatus is small and light enough to be worn by the subject. It is capable of amplifying EEG signals and digitizing them to 22 bits in as many as 150 channels. The apparatus is controlled by software and is plugged into the USB port of a personal computer. This apparatus makes it possible, for the first time, to obtain high-resolution functional EEG images of a thinking brain in a real-life, ambulatory setting outside a research laboratory or hospital.
Gevins, Alan↗
Energy system digitization in the era of AI: A three-layered approach toward carbon neutrality
Not Available
29 ENERGY PLANNING, POLICY, AND ECONOMY↗
Digital System Robustness via Design Constraints: The Lesson of Formal Methods.
Abstract not provided.
Mayo, Jackson↗
Modeling and Design of a Sub-Nyquist PDV Digitization System
Photon-Doppler Velocimetry (PDV) uses interferometry of a transmitted optical signal reflected from a fast-moving device under test (DUT) to generate a product signal at a doppler shifted frequency which is proportional to the velocity of the object being measured. The technique has applications in shock physics, where it is used to measure fast-moving objects over a short lifespan of travel, such as a bullet, shrapnel, or other shock accelerated object.
42 ENGINEERING↗
Digital system detects binary code patterns containing errors
System of square loop magnetic cores associated with code input registers to react to input code patterns by reference to a group of control cores in such a manner that errors are canceled and patterns containing errors are accepted for amplification and processing. This technique improves reception capabilities in PCM telemetry systems.
Muller, R. M.↗
The effect of timing errors in optical digital systems
The effects of imperfect timing in direct detection (non-coherent) optical binary systems using both PPM and on-off keying for bit transmission are investigated. Particular emphasis is placed on specification of timing accuracy, and an examination of system degradation when this accuracy is not attained. Bit error probabilities are shown as a function of timing errors, from which average error probabilities can be computed for specific synchronization methods. Of significant importance is the presence of a residual, or irreducible error probability in both systems, due entirely to the timing system, that cannot be overcome by the data channel.
Gagliardi, R.↗
Testability enhancement in digital system design
A new way of employing hardware redundancy to reduce the number of tests for fault detection in both combinational and synchronous sequential circuits is investigated. An approach is presented for utilizing systematic redundancy to simplify design work. Models for PLM (programmable logic module) and CMM (controllable memory module) are depicted. Systematic design and detection procedures are described. Using these procedures, an easily testable circuit (for stuck faults) can be designed. In contrast to the earlier results on fault detection in logic circuit, two tests are needed to detect any stuck faults of combinational logic circuit. Four tests are necessary and sufficient to detect any stuck faults of elementary logic gates and the malfunction of flip-flops of synchronous sequential circuit using Delay flip-flops or trigger flip-flops.
Chuang, C. S.↗
Toward the assessment of the susceptibility of a digital system to lightning upset
Accomplishments and directions for further research aimed at developing methods for assessing a candidate design of an avionic computer with respect to susceptability to lightning upset are reported. Emphasis is on fault tolerant computers. Both lightning stress and shielding are covered in a review of the electromagnetic environment. Stress characterization, system characterization, upset detection, and positive and negative design features are considered. A first cut theory of comparing candidate designs is presented including tests of comparative susceptability as well as its analysis and simulation. An approach to lightning induced transient fault effects is included.
Tront, J. G.↗