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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

High-Speed On-Board Data Processing for Science Instruments: HOPS

The project called High-Speed On-Board Data Processing for Science Instruments (HOPS) has been funded by NASA Earth Science Technology Office (ESTO) Advanced Information Systems Technology (AIST) program during April, 2012 â€" April, 2015. HOPS is an enabler for science missions with extremely high data processing rates. In this three-year effort of HOPS, Active Sensing of CO2 Emissions over Nights, Days, and Seasons (ASCENDS) and 3-D Winds were of interest in particular. As for ASCENDS, HOPS replaces time domain data processing with frequency domain processing while making the real-time on-board data processing possible. As for 3-D Winds, HOPS offers real-time high-resolution wind profiling with 4,096-point fast Fourier transform (FFT). HOPS is adaptable with quick turn-around time. Since HOPS offers reusable user-friendly computational elements, its FPGA IP Core can be modified for a shorter development period if the algorithm changes. The FPGA and memory bandwidth of HOPS is 20 GB/sec while the typical maximum processor-to-SDRAM bandwidth of the commercial radiation tolerant high-end processors is about 130-150 MB/sec. The inter-board communication bandwidth of HOPS is 4 GB/sec while the effective processor-to-cPCI bandwidth of commercial radiation tolerant high-end boards is about 50-75 MB/sec. Also, HOPS offers VHDL cores for the easy and efficient implementation of ASCENDS and 3-D Winds, and other similar algorithms. A general overview of the 3-year development of HOPS is the goal of this presentation.

Beyon, Jeffrey↗
NASA NTRS2012

NASA Tech Briefs, August 2012

Topics covered include: Mars Science Laboratory Drill; Ultra-Compact Motor Controller; A Reversible Thermally Driven Pump for Use in a Sub-Kelvin Magnetic Refrigerator; Shape Memory Composite Hybrid Hinge; Binding Causes of Printed Wiring Assemblies with Card-Loks; Coring Sample Acquisition Tool; Joining and Assembly of Bulk Metallic Glass Composites Through Capacitive Discharge; 670-GHz Schottky Diode-Based Subharmonic Mixer with CPW Circuits and 70-GHz IF; Self-Nulling Lock-in Detection Electronics for Capacitance Probe Electrometer; Discontinuous Mode Power Supply; Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI; Hardware for Accelerating N-Modular Redundant Systems for High-Reliability Computing; Blocking Filters with Enhanced Throughput for X-Ray Microcalorimetry; High-Thermal-Conductivity Fabrics; Imidazolium-Based Polymeric Materials as Alkaline Anion-Exchange Fuel Cell Membranes; Electrospun Nanofiber Coating of Fiber Materials: A Composite Toughening Approach; Experimental Modeling of Sterilization Effects for Atmospheric Entry Heating on Microorganisms; Saliva Preservative for Diagnostic Purposes; Hands-Free Transcranial Color Doppler Probe; Aerosol and Surface Parameter Retrievals for a Multi-Angle, Multiband Spectrometer LogScope; TraceContract; AIRS Maps from Space Processing Software; POSTMAN: Point of Sail Tacking for Maritime Autonomous Navigation; Space Operations Learning Center; OVERSMART Reporting Tool for Flow Computations Over Large Grid Systems; Large Eddy Simulation (LES) of Particle-Laden Temporal Mixing Layers; Projection of Stabilized Aerial Imagery Onto Digital Elevation Maps for Geo-Rectified and Jitter-Free Viewing; Iterative Transform Phase Diversity: An Image-Based Object and Wavefront Recovery; 3D Drop Size Distribution Extrapolation Algorithm Using a Single Disdrometer; Social Networking Adapted for Distributed Scientific Collaboration; General Methodology for Designing Spacecraft Trajectories; Hemispherical Field-of-View Above-Water Surface Imager for Submarines; and Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly.

Source record↗
NASA NTRS2011

Energy Usage in an Embedded Space Vision Application on a Tiled Architecture

The need for greater autonomy in platforms such as planetary rovers is driving rapidly to codes that far overwhelm the capabilities of conventional space-qualified single core processors to run them in real-time. However, a new generation of potentially space-qualified 2D "tiled" multi-core microprocessor chips is emerging with significant performance potential. Leveraging such inherently parallel hardware for space platforms requires consideration of both time and power limitations - the latter of which is not normally done in conventional parallel computing. This paper takes one such application, Rockster, and analyzes it for energy usage when ported to a multi-core tiled chip such as may come from the Maestro program. The results demonstrate not only the criticality of memory and interconnect in the energy of real-time parallel codes, but also the effects of possible "energy-aware" changes in partitioning and algorithm design.

multi-core processors↗
NASA NTRS1973

An interactive NASTRAN preprocessor

A Langley Research Center version of NASTRAN Level 15.1.0 designed to provide the analyst with an added tool for debugging massive NASTRAN input data is described. The program checks all NASTRAN input data cards and displays on a CRT the graphic representation of the undeformed structure. In addition, the program permits the display and alteration of input data and allows reexecution without physically resubmitting the job. Core requirements on the CDC 6000 computer are approximately 77,000 octal words of central memory.

Smith, W. W.↗
NASA NTRS1996

Performance of NASA Equation Solvers on Computational Mechanics Applications

This paper describes the performance of a new family of NASA-developed equation solvers used for large-scale (i.e. 551,705 equations) structural analysis. To minimize computer time and memory, the solvers are divided by application and matrix characteristics (sparse/dense, real/complex, symmetric/nonsymmetric, size: in-core/out of core) and exploit the hardware features of current and future computers. In this paper, the equation solvers, which are written in FORTRAN, and are therefore easily transportable, are shown to be faster than specialized computer library routines utilizing assembly code. Twenty NASA structural benchmark models with NASA solver timings reside on World Wide Web with a challenge to beat them.

Storaasli, Olaf O.↗
NASA NTRS2013

Remote Memory Access Protocol Target Node Intellectual Property

The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

Haddad, Omar↗
NASA NTRS2017

Dynamic Analysis for a Geared Turbofan Engine with Variable Area Fan Nozzle

Aggressive design goals have been set for future aero-propulsion systems with regards to fuel economy, noise, and emissions. To meet these challenging goals, advanced propulsion concepts are being explored and current operating margins are being re-evaluated to find additional concessions that can be made. One advanced propulsion concept being evaluated is a geared turbofan with a variable area fan nozzle (VAFN), developed by NASA. This engine features a small core, a fan driven by the low pressure turbine through a reduction gearbox, and a shape memory alloy (SMA)-actuated VAFN. The VAFN is designed to allow both a small exit area for efficient operation at cruise, while being able to open wider at high power conditions to reduce backpressure on the fan and ensure a safe level of stall margin is maintained. The VAFN is actuated via a SMA-based system instead of a conventional system to decrease overall weight of the system, however, SMA-based actuators respond relatively slowly, which introduces dynamic issues that are investigated in this work. This paper describes both a control system designed specifically for issues associated with SMAs, and dynamic analysis of the geared turbofan VAFN with the SMA actuators. Also, some future recommendations are provided for this type of propulsion system.

N+3↗
NASA NTRS1969

Adding calcium improves lithium ferrite core

Adding calcium increases uniformity of grain growth over a wide range of sintering temperatures and reduces porosity within the grain. Ferrite cores containing calcium have square hysteresis loops and high curie temperatures, making them useful in coincident current memories of digital electronic computers.

Lessoff, H.↗
NASA NTRS2004

IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA

Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.

single event upset (SEU)↗
NASA NTRS2018

An Investigation of Parallel Programming Techniques Applied to Monte Carlo Simulations for Post-Flight Reconstruction of Spacecraft Trajectory

Parallelizing software to execute on multi-core central processing units (CPUs) and graphics processing units (GPUs) can be challenging. For some fields outside of Computer Science, this transition comes with new issues. For example, memory limitations can require modifications to code not initially developed to run on GPUs. This work applies the Open Multi-Processing (OpenMP) and Open Accelerators (OpenACC) directive-based parallelization strategies on a Monte Carlo simulation approach for trajectory reconstruction enabling it to run on multi-core CPUs and GPUs. Large matrix operations are the most common use of GPUs, which are not present in this algorithm; however, the natural parallelism of independent trajectories in Monte Carlo simulations is exploited. Benchmarking data are presented comparing execution times of the software for single-thread CPUs, multi-thread CPUs with OpenMP, and multi-thread GPUs using OpenACC. These data were collected using nodes with Intel® Xeon® E5-2670 (Sandy Bridge) CPUs enhanced with NVIDIA® Tesla® K40 GPUs on the Pleiades Supercomputer cluster at the National Aeronautics and Space Administration (NASA) Ames Research Center (ARC) and a local Intel® Xeon Phi™ node at NASA Langley Research Center (LaRC).

Williams, R. Anthony↗
NASA NTRS1978

On-board orbit determination for applications satellites

An algorithm for satellite orbit determination is described which would be suitable for use with an on-board computer with limited core storage. The proposed filter is recursive on a pass-by-pass basis and features a fading memory to account for the effect of gravity field error. Only a single pass of Doppler data needs to be stored at any time and the data may be acquired from two reference beacons located within the Continental United States. The results of both simulated data and real data reductions demonstrate that the satellite's position can be determined to within one kilometer when a 4 x 4 recovery field is used.

Morduch, G. E.↗
NASA NTRS2019

Vorago RH-OBC-1 Single Event Effect Characterization Test Report

The Vorago Technologies RH-OBC-1 is a CubeSat Kit Bus compatible single board computer with a Vorago VA10820 ARM Cortex-M0 microcontroller at its core. The board also includes a set of common peripheral integrated circuits, like voltage regulators, non-volatile memories (NVM), an analog-to-digital converter (ADC), a watchdog/supervisor, and a Controller Area Network (CAN) bus transceiver. High-energy proton (200 MeV) testing was conducted at both board and component levels to investigate single-event effects.

CubeSat compatible board↗
NASA NTRS2006

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Berger, Richard↗
NASA NTRS2006

Upset Characterization of the PowerPC405 Hard-core Processor Embedded in Virtex-II Pro Field Programmable Gate Arrays

Shown in this presentation are recent results for the upset susceptibility of the various types of memory elements in the embedded PowerPC405 in the Xilinx V2P40 FPGA. For critical flight designs where configuration upsets are mitigated effectively through appropriate design triplication and configuration scrubbing, these upsets of processor elements can dominate the system error rate. Data from irradiations with both protons and heavy ions are given and compared using available models.

radiation effects↗
NASA NTRS2011

High-Temperature Smart Structures for Engine Noise Reduction and Performance Enhancement

One of key NASA goals is to develop and integrate noise reduction technology to enable unrestricted air transportation service to all communities. One of the technical priorities of this activity has been to account for and reduce noise via propulsion/airframe interactions, identifying advanced concepts to be integrated with the airframe to mitigate these noise-producing mechanisms. An adaptive geometry chevron using embedded smart structures technology offers the possibility of maximizing engine performance while retaining and possibly enhancing the favorable noise characteristics of current designs. New high-temperature shape memory alloy (HTSMA) materials technology enables the devices to operate in both low-temperature (fan) and high-temperature (core) exhaust flows. Chevron-equipped engines have demonstrated reduced noise in testing and operational use. It is desirable to have the noise benefits of chevrons in takeoff/landing conditions, but have them deployed into a minimum drag position for cruise flight. The central feature of the innovation was building on rapidly maturing HTSMA technology to implement a next-generation aircraft noise mitigation system centered on adaptive chevron flow control surfaces. In general, SMA-actuated devices have the potential to enhance the demonstrated noise reduction effectiveness of chevron systems while eliminating the associated performance penalty. The use of structurally integrated smart devices will minimize the mechanical and subsystem complexity of this implementation. The central innovations of the effort entail the modification of prior chevron designs to include a small cut that relaxes structural stiffness without compromising the desired flow characteristics over the surface; the reorientation of SMA actuation devices to apply forces to deflect the chevron tip, exploiting this relaxed stiffness; and the use of high-temperature SMA (HTSMA) materials to enable operation in the demanding core chevron environment. The overall conclusion of these design studies was that the cut chevron concept is a critical enabling step in bringing the variable geometry core chevron within reach. The presence of the cut may be aerodynamically undesirable in some respects, but it is present only when the chevron is not immersed in the core jet exhaust. When deployed, the gap closes as the chevron tip enters the high-speed, high-temperature core stream. Aeroacoustic testing and flow visualization support the contention that this cut is inconsequential to chevron performance.

Quackenbush, Todd R.↗
NASA NTRS2017

Unobtrusive Software and System Health Management with R2U2 on a Parallel MIMD Coprocessor

Dynamic monitoring of software and system health of a complex cyber-physical system requires observers that continuously monitor variables of the embedded software in order to detect anomalies and reason about root causes. There exists a variety of techniques for code instrumentation, but instrumentation might change runtime behavior and could require costly software re-certification. In this paper, we present R2U2E, a novel realization of our real-time, Realizable, Responsive, and Unobtrusive Unit (R2U2). The R2U2E observers are executed in parallel on a dedicated 16-core EPIPHANY co-processor, thereby avoiding additional computational overhead to the system under observation. A DMA-based shared memory access architecture allows R2U2E to operate without any code instrumentation or program interference.

Schumann, Johann↗
NASA NTRS1999

Fast Time-Varying Volume Rendering Using Time-Space Partition (TSP) Tree

We present a new, algorithm for rapid rendering of time-varying volumes. A new hierarchical data structure that is capable of capturing both the temporal and the spatial coherence is proposed. Conventional hierarchical data structures such as octrees are effective in characterizing the homogeneity of the field values existing in the spatial domain. However, when treating time merely as another dimension for a time-varying field, difficulties frequently arise due to the discrepancy between the field's spatial and temporal resolutions. In addition, treating spatial and temporal dimensions equally often prevents the possibility of detecting the coherence that is unique in the temporal domain. Using the proposed data structure, our algorithm can meet the following goals. First, both spatial and temporal coherence are identified and exploited for accelerating the rendering process. Second, our algorithm allows the user to supply the desired error tolerances at run time for the purpose of image-quality/rendering-speed trade-off. Third, the amount of data that are required to be loaded into main memory is reduced, and thus the I/O overhead is minimized. This low I/O overhead makes our algorithm suitable for out-of-core applications.

Shen, Han-Wei↗
NASA NTRS2015

Pi-Sat: A Low Cost Small Satellite and Distributed Spacecraft Mission System Test Platform

Current technology and budget trends indicate a shift in satellite architectures from large, expensive single satellite missions, to small, low cost distributed spacecraft missions. At the center of this shift is the SmallSatCubesat architecture. The primary goal of the Pi-Sat project is to create a low cost, and easy to use Distributed Spacecraft Mission (DSM) test bed to facilitate the research and development of next-generation DSM technologies and concepts. This test bed also serves as a realistic software development platform for Small Satellite and Cubesat architectures. The Pi-Sat is based on the popular $35 Raspberry Pi single board computer featuring a 700Mhz ARM processor, 512MB of RAM, a flash memory card, and a wealth of IO options. The Raspberry Pi runs the Linux operating system and can easily run Code 582s Core Flight System flight software architecture. The low cost and high availability of the Raspberry Pi make it an ideal platform for a Distributed Spacecraft Mission and Cubesat software development. The Pi-Sat models currently include a Pi-Sat 1U Cube, a Pi-Sat Wireless Node, and a Pi-Sat Cubesat processor card.The Pi-Sat project takes advantage of many popular trends in the Maker community including low cost electronics, 3d printing, and rapid prototyping in order to provide a realistic platform for flight software testing, training, and technology development. The Pi-Sat has also provided fantastic hands on training opportunities for NASA summer interns and Pathways students.

Software↗