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Breadboarded circuit is faster and more thorough than software simulator. Elementary fault simulator for AND gate uses three gates and shaft register to simulate stuck-at-one or stuck-at-zero conditions at inputs and output. Experimental results showed hardware fault simulator for microprocessor gave faster results than software simulator, by two orders of magnitude, with one test being applied every 4 microseconds.
A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
Significant problems are faced by astronauts on orbit in the Space Station when trying to locate electrical faults in multi-segment avionics and communication cables. These problems necessitate the development of an automated portable device that will detect and locate cable faults using the pulse-echo technique known as Time Domain Reflectometry. A breadboard time domain reflectometer (TDR) circuit board was designed and developed at the NASA-JSC. The TDR board works in conjunction with a GRiD lap-top computer to automate the fault detection and isolation process. A software program was written to automatically display the nature and location of any possible faults. The breadboard system can isolate open circuit and short circuit faults within two feet in a typical space station cable configuration. Follow-on efforts planned for 1994 will produce a compact, portable prototype Space Station TDR capable of automated switching in multi-conductor cables for high fidelity evaluation. This device has many possible commercial applications, including commercial and military aircraft avionics, cable TV, telephone, communication, information and computer network systems. This paper describes the principle of time domain reflectometry and the methodology for on-orbit avionics utility distribution system repair, utilizing the newly developed device called the Space Station Time Domain Reflectometer (SSTDR).
Quantum computing promises to offer substantial speed-ups over its classical counterpart for certain problems. However, the greatest impediment to realizing its full potential is noise that is inherent to these systems. The widely accepted solution to this challenge is the implementation of fault-tolerant quantum circuits, which is out of reach for current processors. Here we report experiments on a noisy 127-qubit processor and demonstrate the measurement of accurate expectation values for circuit volumes at a scale beyond brute-force classical computation. We argue that this represents evidence for the utility of quantum computing in a pre-fault-tolerant era. These experimental results are enabled by advances in the coherence and calibration of a superconducting processor at this scale and the ability to characterize and controllably manipulate noise across such a large device. We establish the accuracy of the measured expectation values by comparing them with the output of exactly verifiable circuits. In the regime of strong entanglement, the quantum computer provides correct results for which leading classical approximations such as pure-state-based 1D (matrix product states, MPS) and 2D (isometric tensor network states, isoTNS) tensor network methods break down. These experiments demonstrate a foundational tool for the realization of near-term quantum applications.
A power conditioner was developed which used a capacitor diode voltage multiplier to provide a high voltage without the use of a step-up transformer. The power conditioner delivered 1200 Vdc at 100 watts and was operated from a 120 Vdc line. The efficiency was in excess of 90 percent. The component weight was 197 grams. A modified boost-add circuit was used for the regulation. A short circuit protection circuit was used which turns off the drive circuit upon a fault condition, and recovers within 5 ms after removal of the short. High energy density polysulfone capacitors and high speed diodes were used in the multiplier circuit.
Lithium-ion battery systems consist of a varying number of single cells, designed to meet specific application requirements for output voltage and capacity. Effective fault diagnosis in these battery systems is an essential prerequisite for ensuring their safe and reliable operation. To address this need, we introduce a novel model-based fault diagnosis approach that distinguishes itself by leveraging informative structures inherent in battery systems such as architecture, uniformity among the constituent cells, and sparsity of fault occurrences to enhance its fault diagnosis capabilities. The proposed approach formulates a moving horizon estimation (MHE) problem, incorporating such structural information to estimate different fault signals—specifically, internal short circuits, external short circuits, and voltage and current sensors faults. We conduct various simulations to evaluate the performance of the proposed approach under different fault types and magnitudes. The obtained results validate the proposed approach and promise effective fault diagnosis for battery systems.
Fast and accurate methods of fault detection and isolation are a pre-emptive measure in multiterminal dc (MTdc) systems. Zonal isolation of faults is necessary to prevent any misopertation of the dc breakers that can lead to a shutdown of the network. Existing techniques require fast-communication or data synchronization methods have their own disadvantages. This article proposes a method for efficient fault zone isolation without the need of a communication link that prevents any misoperation of the dc breakers in a radial MTdc. This method provides individual local measurement-based control to the hybrid dc circuit breakers (dcCB). Faults created outside the zone of protection for a breaker create a change in the rate of change of current or voltage leading to misoperation. To avoid detection using a fixed threshold, an adaptive threshold based approach is suggested that updates the threshold based on the present operating status. Sensitivity analysis by varying the current limiting inductance and fault location is performed. In conclusion, a three terminal radial model of an MTdc is used for zonal isolation using power system computer aided design/electromagnetic transients including dc.
This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.
A method and apparatus for testing the operation of a complex stabilization circuit in a closed loop system is presented. The method is comprised of a programmed analog or digital computing system for implementing the transfer function of a load thereby providing a predictable load. The digital computing system employs a table stored in a microprocessor in which precomputed values of the load transfer function are stored for values of input signal from the stabilization circuit over the range of interest. This technique may be used not only for isolating faults in the stabilization circuit, but also for analyzing a fault in a faulty load by so varying parameters of the computing system as to simulate operation of the actual load with the fault.
Fault-tolerant-microcomputer concept based on enhancing "simple" computer with redundancy and self-checking logic circuits detect hardware faults. Interface and checking logic and redundant processors confer on 16-bit microcomputer ability to check itself for hardware faults. Checking circuitry also checks itself. Concept of self-checking complementary pairs (SCCP's) employed throughout ICL unit.
Concatenated bosonic-stabilizer codes have recently gained prominence as promising candidates for achieving low-overhead fault-tolerant quantum computing in the long term. In such systems, analog information obtained from the syndrome measurements of an inner bosonic code is used to inform decoding for an outer code layer consisting of a discrete-variable stabilizer code such as a surface code. The use of Quantum Low-Density Parity Check (QLDPC) codes as an outer code is of particular interest due to the significantly higher encoding rates offered by these code families, leading to a further reduction in overhead for large-scale quantum computing. Recent works have investigated the performance of QLDPC-GKP codes in detail, and the use of analog information from the inner code significantly boosts decoder performance. However, the noise models assumed in these works are typically limited to depolarizing or phenomenological noise. In this paper, we investigate the performance of QLDPC-GKP concatenated codes under circuit-level noise, based on a model introduced by Noh et al. in the context of the surface-GKP code. To demonstrate the performance boost from analog information, we investigate three scenarios: (a) decoding without soft information, (b) decoding with precomputed error probabilities but without real-time soft information, and (c) decoding with real-time soft information obtained from round-to-round decoding of the inner GKP code. Results show minimal improvement between (a) and (b), but a significant boost in (c), indicating that real-time soft information is critical for concatenated decoding under circuit-level noise. We also study the effect of measurement schedules with varying depths and show that using a schedule with minimum depth is essential for obtaining reliable soft information from the inner code.
Arbitrary single gate failures diagnosis in combinational logic circuits not requiring fault table construction
The concept of Boolean integration is developed, and different Boolean integral operators are introduced. Given the changes in a desired function in terms of the changes in its arguments, the ways of 'integrating' (i.e. realizing) such a function, if it exists, are presented. The necessary and sufficient conditions for integrating, in different senses, the expression specifying the changes are obtained. Boolean calculus has applications in the design of logic circuits and in fault analysis.
A switchgear controller utilizing a microcontroller is described. The primary goal was to mimic the functions and performance of the generic controller board with a microcontroller board which will cause the power automation system to consume less power. The code for the microcontroller implementation on a development board has been developed, and the signal conditioning for the signals to the microcontroller has been designed and tested. The implementation of this decision system for data gathering, command control, fault detection, and circuit protection, when compared to other implementations, provides more functions and better response while reducing weight, volume, and power consumption.
The Navy is experiencing a severe aircraft electrical wiring maintenance problem as a result of the extensive use of an aromatic polyimide insulation that is deteriorating at a rate that was unexpected when this wire was initially selected. This problem has significantly affected readiness, reliability, and safety and has greatly increased the cost of ownership of Naval aircraft. Failures in wire harnesses have exhibited arcing and burning that will propagate drastically, to the interruption of many electrical circuits from a fault initiated by the failure of deteriorating wires. There is an urgent need for a capability to schedule aircraft rewiring in an orderly manner with a logically derived determination of which aircraft have aged to the point of absolute necessity. Excessive maintenance was demonstrated to result from the accelerated aging due to the parameters of moisture, temperature, and strain that exist in the Naval Aircraft environment. Laboratory studies have demonstrated that MIL-W-81381 wire insulation when aged at high humidities followed the classical Arrhenius thermal aging relationship. In an extension of the project a multifactor formula was developed that is now capable of predicting life under varying conditions of these service parameters. An automated test system has also been developed to analyze the degree of deterioration that has occurred in wires taken from an aircraft in order to obtain an assessment of remaining life. Since it is both physically and financially impossible to replace the wiring in all the Navy's aircraft at once, this system will permit expedient scheduling so that those aircraft that are most probable to have wiring failure problems can be overhauled first.
Self-Validating Thermocouple (SVT) Systems capable of detecting sensor probe open circuits, short circuits, and unnoticeable faults such as a probe debonding and probe degradation are useful in the measurement of temperatures. SVT Systems provide such capabilities by incorporating a heating or excitation element into the measuring junction of the thermocouple. By heating the measuring junction and observing the decay time for the detected DC voltage signal, it is possible to indicate whether the thermocouple is bonded or debonded. A change in the thermal transfer function of the thermocouple system causes a change in the rise and decay times of the thermocouple output. Incorporation of the excitation element does not interfere with normal thermocouple operation, thus further allowing traditional validation procedures as well.
In one aspect, a hybrid circuit protection device for current-limiting a fault current between a source and a load during a fault is provided. The hybrid circuit protection device includes an input configured to couple to the source, an output configured to couple to the load, a return configured to couple the source to the load, a main switch configured to selectively couple the input to the output, a switching network coupled in parallel with the main switch, and a controller. The controller is configured to determine that the main switch has opened in response to the fault current, where the fault current has an initial value, and activate the switching network to current-limit the fault current to less than the initial value during the fault.
The time interval between the occurrence of a fault and the detection of the error caused by the fault is divided by the generation of that error into two parts: fault latency and error latency. Since the moment of error generation is not directly observable, all related works in the literature have dealt with only the sum of fault and error latencies, thereby making the analysis of their separate effects impossible. To remedy this deficiency, (1) a new methodology for indirectly measuring fault latency is presented; the distribution of fault latency is derived from the methodology; and (3) the knowledge of fault latency is applied to the analysis of two important examples. The proposed methodology has been implemented for measuring fault latency in the Fault-Tolerant Multiprocessor (FTMP) at the NASA Airlab. The experimental results show wide variations in the mean fault latencies of different function circuits within FTMP. Also, the measured distributions of fault latency are shown to have monotone hazard rates. Consequently, Gamma and Weibull distributions are selected for the least-squares fit as the distribution of fault latency.