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Port and optimize the CEED software stack to Aurora/Frontier EA (ECP Milestone Report)
The goal of this milestone was to port the CEED software stack, including Nek, MFEM and libCEED to the Frontier and Aurora early access hardware, work on optimizing the performance on AMD and Intel GPUs, and demonstrate impact in CEED-enabled ECP applications. As part of this milestone, we also performed a number of other activities, including continued optimizations for CEED applications at scale on Summit, performance evaluation on non-ECP hardware, including the Fugaku’s A64FX chip and the NVIDIA A100 GPU architecture, exploring the use of just-in-time compilations in applications at scale and potential of mixed precision optimizations in the CEED discretization and solver algorithms, and more. During the milestone period, the CEED team released new versions of 6 of its packages, including major releases of MFEM, NekRS and OCCA. We also organized the fifth CEED Annual meeting (CEED5AM) which included nearly 100 researchers from national labs, universities and industry.
Nanoscale Electronic Transparency of Wafer-Scale Hexagonal Boron Nitride
We report monolayer hexagonal boron nitride (hBN) has attracted interest as an ultrathin tunnel barrier or environmental protection layer. Recently, wafer-scale hBN growth on Cu(111) was developed for semiconductor chip applications. For basic research and technology, understanding how hBN perturbs underlying electronically active layers is critical. Encouragingly, hBN/Cu(111) has been shown to preserve the Cu(111) surface state (SS), but it was unknown how tunneling into this SS through hBN varies spatially. Here, we demonstrate that the Cu(111) SS under wafer-scale hBN is homogeneous in energy and spectral weight over nanometer length scales and across atomic terraces. In contrast, a new spectral feature-not seen on bare Cu(111)-varies with atomic registry and shares the spatial periodicity of the hBN/Cu(111) moiré. This work demonstrates that, for some 2D electron systems, an hBN overlayer can act as a protective yet remarkably transparent window on fragile low-energy electronic structure below.
An Algebraic Quantum Circuit Compression Algorithm for Hamiltonian Simulation
Quantum computing is a promising technology that harnesses the peculiarities of quantum mechanics to deliver computational speedups for some problems that are intractable to solve on a classical computer. Current generation noisy intermediate-scale quantum (NISQ) computers are severely limited in terms of chip size and error rates. Shallow quantum circuits with uncomplicated topologies are essential for successful applications in the NISQ era. In this work, based on matrix analysis, we derive localized circuit transformations to efficiently compress quantum circuits for simulation of certain spin Hamiltonians known as free fermions. The depth of the compressed circuits is independent of simulation time and grows linearly with the number of spins. The proposed numerical circuit compression algorithm behaves backward stable and scales cubically in the number of spins enabling circuit synthesis beyond O(10 3 ) spins. The resulting quantum circuits have a simple nearest-neighbor topology, which makes them ideally suited for NISQ devices.
The design and construction of the Chips water Cherenkov neutrino detector
Chips (CHerenkov detectors In mine PitS) was a prototype large-scale water Cherenkov detector located in northern Minnesota. The main aim of the R&D project was to demonstrate that construction costs of neutrino oscillation detectors could be reduced by at least an order of magnitude compared to other equivalent experiments. This article presents design features of the Chips detector along with details of the implementation and deployment of the prototype. While issues during and after the deployment of the detector prevented data taking, a number of key concepts and designs were successfully demonstrated.
Microfabricated Ion Traps on Sapphire for Larger Trap Areas and Higher Qubit Count
Surface ion traps are a promising platform for quantum computing due to their potential to store large numbers of ions that can be addressed by electrical and optical control signals in order to implement quantum algorithms. Increasing the power of the quantum computer requires increasing the number of ions, but this poses a significant challenge in that it leads to a non-linear increase in on-chip power dissipation. The primary contributor to this power scaling in current devices is the capacitance between the radio frequency (RF) electrode and the metal plane that shields the silicon substrate from the RF signals applied to it. Silicon has traditionally been chosen for the substrate material for compatibility with the processing required for multi-metal-level traps. In this work, we address these capacitance and fabrication challenges by replacing the commonly used silicon substrate with an insulating sapphire substrate to fabricate a multi-metal-level ion trap, while still employing common semiconductor manufacturing techniques. This change in substrate allows the design to remove the metal shielding from the device design, reducing the capacitance of the RF electrode. The electrical characteristics of these traps were measured, specifically trap impedance, capacitance, and voltage breakdown, and compared to nearly identical silicon trap devices. Finally, we used laser cutting techniques to shape a sapphire wafer into bowtie shapes matching silicon traps previously fabricated at Sandia National Labs to explore solutions for integrating sapphire substrates into non-rectangular ion trap designs.
Leveraging Quantum Sensors for Dark Matter Detection
Recent measurements have demonstrated that superconducting qubit decoherence is affected by radiation. As a result, many groups around the world are working to better understand the relationship between different types of radiation and qubit response. This crucial to quantum error correction because radiation can cause correlated loss of information across multiple qubits on a chip, defeating error correction algorithms. Additionally, the fundamental energy scale at which superconducting qubits operate may enable their development as meV-scale detectors for HEP applications, such as the direct detection of dark matter. At Fermilab, we have two world-class underground facilities which are already being used to study this problem: NEXUS and QUIET. I will present on results from operating superconducting qubits in each of these facilities, and the potential implications towards utilizing qubits as sensors for a novel dark matter detector.
Leveraging Quantum Sensors for Dark Matter Detection
Recent measurements have demonstrated that superconducting qubit decoherence is affected by radiation. As a result, many groups around the world are working to better understand the relationship between different types of radiation and qubit response. This crucial to quantum error correction because radiation can cause correlated loss of information across multiple qubits on a chip, defeating error correction algorithms. Additionally, the fundamental energy scale at which superconducting qubits operate may enable their development as meV-scale detectors for HEP applications, such as the direct detection of dark matter. At Fermilab, we have two world-class underground facilities which are already being used to study this problem: NEXUS and QUIET. I will present on results from operating superconducting qubits in each of these facilities, and the potential implications towards utilizing qubits as sensors for a novel dark matter detector.
A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization
A self-powered IoT system-on-chip (SoC) reduces power to sub-μw and employs multiple power-management techniques to trade-off ultra-low power (ULP), higher performance, smaller energy harvester footprint, and longer operating lifetime. Minimum Energy Point Tracking (MEPT) [1]–[4] keeps an SoC operating at the minimum energy point (MEP) to enhance system lifetime. Previous sample-and-hold MEPT schemes need frequent voltage comparisons and a high-frequency clock that increases power [2]. Current-ratio-based MEPT relies on specialized CMOS technology for body-bias tuning [3]. A switched-capacitor-based MEPT can achieve energy minimization at a targeted performance [4], but it uses a 30MHz clock witμW power consumption and low power efficiency. For ULP IoT applications, SoCs need to have ultra-low quiescent power, high efficiency for energy delivery, performance scaling based on available energy, and energy minimization to increase system lifetime. In this work, we propose an ULP IoT SoC with a triple-mode power management unit (PMU) that integrates energy-performance scaling, event-driven fast DVFS, and MEPT features to improve the system energy efficiency, as shown in Fig. 13.8.1. This work achieves a minimum 194nW power consumption for the SoC and 5.2nW quiescent power for the PMU with a 92.6% peak efficiency and >10 4 dynamic range. The timing waveform in Fig. 13.8.1 (bottom), demonstrates the transition of the three modes including energy aware (EA), performance aware (PA), and MEPT based on event priority and input voltage level which reflects the energy availability. As such, the system energy consumption and performance could be well-balanced based on both the input and output conditions.
Scaling Superconducting Quantum Computers with Chiplet Architectures
Fixed-frequency transmon quantum computers (QCs) have advanced in coherence times, addressability, and gate fidelities. Unfortunately, these devices are restricted by the number of on-chip qubits, capping processing power and slowing progress toward fault-tolerance. Although emerging transmon devices feature over 100 qubits, building QCs large enough for meaningful demonstrations of quantum advantage requires overcoming many design challenges. For example, today’s transmon qubits suffer from significant variation due to limited precision in fabrication. As a result, barring significant improvements in current fabrication techniques, scaling QCs by building ever larger individual chips with more qubits is hampered by device variation. Severe device variation that degrades QC performance is referred to as a defect. Here, we focus on a specific defect known as a frequency collision. When transmon frequencies collide, their difference falls within a range that limits two-qubit gate fidelity. Frequency collisions occur with greater probability on larger QCs, causing collision-free yields to decline as the number of on-chip qubits increases. As a solution, we propose exploiting the higher yields associated with smaller QCs by integrating quantum chiplets within quantum multi-chip modules (MCMs). Yield, gate performance, and application-based analysis show the feasibility of QC scaling through modularity. Our results demonstrate that chiplet architectures, relative to monolithic designs, benefit from average yield improvements ranging from 9.6 – 92.6 × for ≲5 qubit machines. In addition, our simulations explore the design space of chiplet systems and discover configurations that demonstrate average two-qubit gate infidelity reductions that are at best 0.815 × their monolithic counterpart. Lastly, we observe that carefully-selected modular systems achieve fidelity improvements on a range of benchmark circuits.
Microfabricated Devices and Ion Trapping Capabilities
Next generation ion traps will likely need to support tens if not hundreds of ions in order to achieve several logical qubits. As we scale to those sizes, the same problems we face now – rf dissipation, control I/O, and optical access – will only grow and become more complicated. While many of these challenges can potentially be solved with technology integration, independently researching the feasibility of that integration and other solutions may help reduce the time and risk in scaling up to larger traps, by testing on smaller less complex devices. We should also consider other fabrication techniques that may help scale to larger devices, such as: through-substrate-vias (TSVs), different metal coatings, exotic rf routing, on chip laser sources, or even a secondary macroscopic trap to reload ions from. To have these technologies ready for full scale integration when we need them, ion traps with some of these capabilities need to be produced now. Developing the rigorous fabrication methods for producing reliable traps takes time and experimentation. We propose developing larger ion traps and reliable integrated technology in conjunction to make both available faster.
SPT-SLIM: Line Intensity Mapping with the South Pole Telescope
Line-intensity mapping (LIM) at millimeter wavelengths is a powerful emerging probe of the large-scale structure of the Universe, but achieving meaningful constraints on cosmological parameters with LIM requires focal planes with orders of magnitudes more detectors than existing instruments. SPT-SLIM is an upcoming experiment to demonstrate LIM observations of CO at 0.5 < z < 2.0 using on-chip spectrometers with kinetic inductance detectors (KIDs), a new technology that enables scaling to the much larger arrays of detectors needed to probe cosmology. I will describe the overall experimental design and specific goals of SPT-SLIM. In addition, I will highlight results of the detector and readout electronics development for SPT-SLIM and the status of the camera integration and commissioning in the lab.
System-on-chip integrated circuit technology applications on the DIII-D tokamak for multi-field measurements
Several mm-wave diagnostics on the DIII-D tokamak provide multi-scale and multi-dimensional measurements of plasma profile evolution and turbulence fluctuations. Mm-wave fusion plasma diagnostics that adopt system-on-chip integrated circuit technology can provide better space utilization, flexible installation, and improved sensitivity. In order to further extend this technology for additional fusion facilities with a higher toroidal magnetic field, V-band (55–75 GHz) and F-band (90–140 GHz) chips for Microwave Imaging Reflectometer (MIR) and Electron Cyclotron Emission Imaging (ECEI) instruments are developed and tested in the Davis Millimeter Wave Research Center (DMRC). Current measurement data show that correlation between these SoC-based diagnostic instruments with other state-of-the-art diagnostics enables co-located multi-field turbulence fluctuation measurement.
Low‐Loss Far‐Infrared Surface Phonon Polaritons in Suspended SrTiO 3 Nanomembranes
Phonon polaritons (PhPs), excitations arising from the coupling of light with lattice vibrations, enable light confinement and local field enhancement, which is essential for various photonic and thermal applications. To date, PhPs with high confinement and low loss are mainly observed in the mid-infrared regime and mostly in manually exfoliated flakes of van der Waals (vdW) materials. In this work, the existence of low-loss, thickness-tunable phonon polaritons in the far-infrared regime within transferable freestanding SrTiO 3 membranes synthesized through a scalable approach, achieving high figures of merit is demonstrated, which are comparable to the previous record values from the vdW materials. Leveraging atomic precision in thickness control, large dimensions, and compatibility with mature oxide electronics, functional oxide membranes present a promising large-scale 2D platform alternative to vdW materials for on-chip polaritonic technologies in the infrared regime.
Characterization of superconducting through-silicon vias as capacitive elements in quantum circuits
The large physical size of superconducting qubits and their associated on-chip control structures presents a practical challenge toward building a large-scale quantum computer. In particular, transmons require a high-quality-factor shunting capacitance that is typically achieved by using a large coplanar capacitor. Other components, such as superconducting microwave resonators used for qubit state readout, are typically constructed from coplanar waveguides, which are millimeters in length. Here, we use compact superconducting through-silicon vias to realize lumped-element capacitors in both qubits and readout resonators to significantly reduce the on-chip footprint of both of these circuit elements. We measure two types of devices to show that through-silicon vias are of sufficient quality to be used as capacitive circuit elements and provide a significant reduction in size over existing approaches.
A 3D-Printed Millimeter-Wave Inline Waveguide-to-Coplanar-Waveguide Transition to Enable Dense Spectrometer Arrays for Intensity Mapping Surveys
We present a 3D-printed millimeter-wave, octave-bandwidth, in-line waveguide-to-coplanar-waveguide transition designed to enable focal planes with dense arrays of on-chip spectrometers. These arrays will enable compelling surveys of the large-scale structure of the universe through millimeter-wave intensity mapping. The transition consists of a four-step ridge-waveguide transformer that couples light from a rectangular waveguide onto a coplanar waveguide via an electrical connection made with indium bump bonds. We develop a tolerance-aware optimization approach to identify high-performance transition geometries that are robust to manufacturing variations; the same formulation can be applied to other tolerance-sensitive design problems. We also describe the implementation of a custom apparatus and procedure for bump-bonding a silicon chip to a metallized 3D-printed component. We detail the fabrication of the coplanar waveguide chip and three-dimensional waveguide structure, simulations and metrology of a test device, and room temperature reflectance measurements of this device. The room temperature metrology and reflection measurements are consistent with a model that predicts a coupling efficiency of $\mathord{\sim} 95\%$ at cryogenic temperatures in the 85-170 GHz frequency range.
COLLABORATIVE DEVELOPMENT PROJECTS - PHOTONIC MEMORY CONTROLLER MODULE (P-MCM)
As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high-performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM).