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Results for “SEMICONDUCTOR DEVICE”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Electrostatic harvester device

An electrostatic harvester device for charging an energy storage device is provided. The electrostatic harvester device comprises an inductor, a variable capacitor device, a semiconductor device, and a plurality of transistors. The inductor is operable to receive electric charge and store the electric charge. The variable capacitor device is configured to receive electric charge from the inductor and to change capacitance in response to physical stimulation. The semiconductor device is operable to allow electric current to flow from the variable capacitor device. The transistors are operable to connect at least two of the aforementioned devices. At least one of the transistors comprises at least one of gallium nitride or aluminum gallium nitride.

Wilson, Amy Charlene↗
DOE OSTI2014

Plated lamination structures for integrated magnetic devices

Semiconductor integrated magnetic devices such as inductors, transformers, etc., having laminated magnetic-insulator stack structures are provided, wherein the laminated magnetic-insulator stack structures are formed using electroplating techniques. For example, an integrated laminated magnetic device includes a multilayer stack structure having alternating magnetic and insulating layers formed on a substrate, wherein each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by an insulating layer, and a local shorting structure to electrically connect each magnetic layer in the multilayer stack structure to an underlying magnetic layer in the multilayer stack structure to facilitate electroplating of the magnetic layers using an underlying conductive layer (magnetic or seed layer) in the stack as an electrical cathode/anode for each electroplated magnetic layer in the stack structure.

42 ENGINEERING↗
DOE OSTI2024

Thermal scanning probe and laser lithography for patterning nanowire based quantum devices

Semiconductor nanowire (NW) quantum devices offer a promising path for the pursuit and investigation of topologically-protected quantum states, and superconducting and spin-based qubits that can be controlled using electric fields. Theoretical investigations into the impact of disorder on the attainment of dependable topological states in semiconducting nanowires with large spin–orbit coupling and g-factor highlight the critical need for improvements in both growth processes and nanofabrication techniques. In this work, we used a hybrid lithography tool for both the high-resolution thermal scanning probe lithography and high-throughput direct laser writing of quantum devices based on thin InSb nanowires with contact spacing of 200 nm. Electrical characterization demonstrates quasi-ballistic transport. The methodology outlined in this study has the potential to reduce the impact of disorder caused by fabrication processes in quantum devices based on 1D semiconductors.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

42 ENGINEERING↗
DOE OSTI2014

Sintered silver joints via controlled topography of electronic packaging subcomponents

Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.

36 MATERIALS SCIENCE↗
DOE OSTI2017

Over-voltage protection system and method

An over-voltage protection system includes an electronic valve connected across two terminals of a circuit and an over-voltage detection circuit connected across one of the plurality of semiconductor devices for detecting an over-voltage across the circuit. The electronic valve includes a plurality of semiconductor devices connected in series. The over-voltage detection circuit includes a voltage divider circuit connected to a break-over diode in a way to provide a representative low voltage to the break-over diode and an optocoupler configured to receive a current from the break-over diode when the representative low voltage exceeds a threshold voltage of the break-over diode indicating an over-voltage condition. The representative low voltage provided to the break-over diode represents a voltage across the one semiconductor device. A plurality of self-powered gate drive circuits are connected to the plurality of semiconductor devices, wherein the plurality of self-powered gate drive circuits receive over-voltage triggering pulses from the optocoupler during the over-voltage condition and switch on the plurality of semiconductor devices to bypass the circuit.

42 ENGINEERING↗
DOE OSTI2015

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga{sub 0.97}N{sub 0.9}O{sub 0.09} is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga{sub 0.97}N{sub 0.9}O{sub 0.09} of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4 M HCl, 100 °C and pulp density of 100 kg/m{sup 3,} respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. - Highlights: • Waste MOCVD dust is treated through mechanochemical leaching. • GaN is hardly leached, and converted to NaGaO{sub 2} through ball milling and annealing. • Process for gallium recovery from waste MOCVD dust has been developed. • Thermal analysis and phase properties of GaN to Ga{sub 2}O{sub 3} and GaN to NaGaO{sub 2} is revealed. • Solid-state chemistry involved in this process is reported.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Atomic Precision Processing of Two-Dimensional Materials for Next-Generation Microelectronics

The growth of the information era economy is driving the pursuit of advanced materials for microelectronics, spurred by exploration into “Beyond CMOS” and “More than Moore” paradigms. Atomically thin 2D materials, such as transition metal dichalcogenides (TMDCs), show great potential for next-generation microelectronics due to their properties and defect engineering capabilities. This perspective delves into atomic precision processing (APP) techniques like atomic layer deposition (ALD), epitaxy, atomic layer etching (ALE), and atomic precision advanced manufacturing (APAM) for the fabrication and modification of 2D materials, essential for future semiconductor devices. Additive APP methods like ALD and epitaxy provide precise control over composition, crystallinity, and thickness at the atomic scale, facilitating high-performance device integration. Subtractive APP techniques, such as ALE, focus on atomic-scale etching control for 2D material functionality and manufacturing. In APAM, modification techniques aim at atomic-scale defect control, offering tailored device functions and improved performance. Achieving optimal performance and energy efficiency in 2D material-based microelectronics requires a comprehensive approach encompassing fundamental understanding, process modeling, and high-throughput metrology. Finally, the outlook for APP in 2D materials is promising, with ongoing developments poised to impact manufacturing and fundamental materials science. Integration with advanced metrology and codesign frameworks will accelerate the realization of next-generation microelectronics enabled by 2D materials.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Science challenges and research opportunities for plasma applications in microelectronics

Low-temperature plasmas (LTPs) are essential to manufacturing devices in the semiconductor industry, from creating extreme ultraviolet photons used in the most advanced lithography to thin film etching, deposition, and surface modifications. It is estimated that 40%–45% of all process steps needed to manufacture semiconductor devices use LTPs in one form or another. LTPs have been an enabling technology in the multidecade progression of the shrinking of device dimensions, often referred to as Moore’s law. New challenges in circuit and device design, novel materials, and increasing demands to achieve environmentally benign processing technologies require advances in plasma technology beyond the current state-of-the-art. The Department of Energy Office of Science Fusion Energy Sciences held a workshop titled Plasma Science for Microelectronics Nanofabrication in August 2022 to discuss the plasma science challenges and technical barriers that need to be overcome to continue to develop the innovative plasma technologies required to support and advance the semiconductor industry. One of the key outcomes of the workshop was identifying a set of priority research opportunities (PROs) to focus attention on the most strategic plasma science challenges to address to benefit the semiconductor industry. For each PRO, scientific challenges and recommended strategies to address those challenges were identified. Furthermore, this article summarizes the PROs identified by the workshop participants.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

42 ENGINEERING↗
DOE OSTI2018

Development of a Physical-Topological Model for the Response of a High-Power Vertical DMOS Transistor to the Effect of Pulsed Gamma-Radiation

A method for developing models of semiconductor devices with two-dimensional nonuniform concentration profiles of donors and acceptors in working regions of a semiconductor device structure is for the first time proposed based on a complex of physical-topological modeling of charge carrier transport and process simulation of the forming processes of the device structure. The application of process simulation is due to the need to correctly define the parameters of the semiconductor device structure, which are used as initial data to calculate the electron transport according to the physical-topological model. The parameters of production processes of ion implantation, diffusion, and lithography, which were refined during process simulation, are determined for a high-power metal—oxide—semiconductor (MOS) transistor forming by the double diffusion method in accordance with known electrical characteristics and measured geometrical sizes of the structure. This results in two-dimensional distribution profiles of donors and acceptors in p–n junctions necessary to calculate the transistor breakdown under the effect of pulsed γ radiation. Breakdown processes are modeled with the help of the physical-topological model based on the Poisson and continuity equations as well as expressions for the diffusion and drift current densities in the transistor. Accounting for carriers formed at the instant of γ irradiation is implemented by the introduction of the dependence of the generation coefficient of electron–hole pairs on the radiation-dose power. The results of calculations correlate well with the experimental data, which makes it possible to give a conclusion regarding the adequacy of the proposed complex model.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Low-energy electro- and photo-emission spectroscopy of GaN materials and devices

In hot-electron semiconductor devices, carrier transport extends over a wide range of conduction states, which often includes multiple satellite valleys. Electrical measurements can hardly give access to the transport processes over such a wide range without resorting to models and simulations. An alternative experimental approach however exists which is based on low-energy electron spectroscopy and provides, in a number of cases, very direct and selective information on hot-electron transport mechanisms. Recent results obtained in GaN crystals and devices by electron emission spectroscopy are discussed. Using near-band-gap photoemission, the energy position of the first satellite valley in wurtzite GaN is directly determined. By electro-emission spectroscopy, we show that the measurement of the electron spectrum emitted from a GaN p-n junction and InGaN/GaN light-emitting diodes (LEDs) under electrical injection of carriers provides a direct observation of transport processes in these devices. In particular, at high injected current density, high-energy features appear in the electro-emission spectrum of the LEDs showing that Auger electrons are being generated in the active region. These measurements allow us identifying the microscopic mechanism responsible for droop which represents a major hurdle for widespread adoption of solid-state lighting.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Energy storage device with large charge separation

High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach. The first aspect is to provide high density energy storage in semiconductor devices based on formation of a plasma in the semiconductor. The second aspect is to provide high density energy storage based on charge separation in a p-n junction.

25 ENERGY STORAGE↗
DOE OSTI2018

Energy storage device with large charge separation

High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach. The first aspect is to provide high density energy storage in semiconductor devices based on formation of a plasma in the semiconductor. The second aspect is to provide high density energy storage based on charge separation in a p-n junction.

25 ENERGY STORAGE↗
DOE OSTI2021

Optical coupler for heterogeneous integration

In an optical apparatus, an introduced semiconductor device is heterointegrated on a silicon-based platform containing a silicon-based waveguide. A polymeric waveguide is optically coupled to the introduced semiconductor device and overlies at least a portion of the silicon-based waveguide. The polymeric waveguide is conformed as a multimode interference (MMI) coupler between the introduced semiconductor device and the silicon-based waveguide. At least the polymeric waveguide, and in embodiments, also the silicon-based waveguide, is tapered with a shape that effectuates optical coupling to the silicon-based waveguide.

Gehl, Michael↗
DOE OSTI2019

Gas Ingress and Egress of MEMS Multi-Chip Modules and MEMS Devices

Hermetic microcircuit packaging was the dominant method of protecting semiconductor devices in the 1960s and 1970s. After losing majority market sectors to plastic encapsulated microelectronics over the last a few decades, hermetic packaging remains the preferred method of protecting semiconductor devices for critical applications such as in military, space, and medical fields, where components and systems are required to serve for several decades. MEMS devices impose additional challenges to packaging by requiring specific internal cavity pressures to function properly or deliver the needed quality (Q) factors. In MEMS multichip modules, internal pressure requirement conflicts arise when different MEMS devices require different internal gases and pressures. The authors developed a closed-formed equation to model pressure changes of hermetic enclosures due to gas ingression. This article expands the authors mathematical model to calculate gas pressure of a MEMS multichip module package as well as those of MEMS devices inside the multichip module package. These equations are not only capable of calculating service lifetimes of MEMS devices and multi-chip modules but can also help develop MEMS device packaging strategies to extend the service life of MEMS multi-chip modules.

36 MATERIALS SCIENCE↗