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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Cryogenic electronics for noble liquid neutrino detectors

In this paper we present the general features of cryogenic (or “cold”) electronics for noble liquid time projection chambers, with design principles and details for neutrino physics, a brief history of the technology and details of recent research and development that is driving the design of the detectors under construction. Finally, some comments on future R&D envisioned and the impact of this work on other fields is described. “Cold” in the context of this work applies to CMOS devices operated at 77 K and above, at liquids temperatures of LAr (89 K), LKr (125 K) and LXe (165 K), with most of the tests performed in, or at LN 2 (77 K). Additionally, the paper is concentrated on the design of cold electronics for large liquid argon TPCs, those that have been successfully operated, MicroBooNE and ProtoDUNE, and those designed or under construction, such as SBND and DUNE first and second 10 kton modules. The high performance achieved with MicroBooNE and ProtoDUNE – a high signal-to-noise ratio combined with high stability of response – is mainly due to the integral approach to design and construction of sensing electrodes with cold readout electronics in a modular approach with the cryostat signal feed-throughs incorporating warm interface electronics into a Faraday cage with the cryostat. The integral concept is described in some detail in this paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Magnetic triggering — time-resolved characterisation of silicon strip modules in the presence of switching DC-DC converters

Modules for the ATLAS Inner Tracker (ITk) strip tracker include a DC-DC converter circuit glued directly to the silicon sensor which converts the 11 V supplied to the module to the 1.5 V required for the operation of the readout chips. The DC-DC converter unit, consisting of a copper solenoid and custom ASIC, is located directly above the silicon strip sensor and therefore needs to be shielded to protect the sensor from EMI noise created during the operation of the circuit. Despite dedicated shielding, consisting of an aluminium shield box with continuous solder seams encompassing the surface components and a copper layer in the PCB beneath it, module channels connected to sensor strips located beneath the converter circuit were found to show a noise increase. While the DC-DC converter unit causing the underlying EMI noise operates at a frequency of 2 MHz, module characterisation measurements for ITk strip tracker modules are typically performed asynchronously to the DC-DC switching and are therefore averaged over the full range of time bins with respect to the converter frequency. In order to investigate the time dependence of the noise injection relative to the DC-DC switching frequency, a dedicated setup to understand the time-resolved performance change in modules was developed. By using a magnetic field probe to measure the field leaking through the shield box and triggering on its rising edge, data taking could be synchronised with the DC-DC switching. This paper illustrates the concept and setup of such time-resolved performance measurements using magnetic triggering and presents results for the observed effects on signal and noise for ATLAS ITk strip modules from both laboratory and beam tests.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Event-driven readout development: testing of the EDWARD65P1 chip with integrated event generators

Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven readout architecture, the front-end in each pixel was replaced by a hardware generator to verify readout performance, ensuring no data loss, consistent priority handling, and speed verification. Here, this generator produces Poisson-distributed readout requests with individually tunable rates per pixel via a digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is a 32×32 pixel matrix with a 100 μm pitch, equipped with digital event generators simulating radiation hits at user-defined rates. Test results for this new design are presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

The VMM3a ASIC

The VMM3a is a custom low-noise Application Specific Integrated Circuit. It is intended to be used in the front end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130 nm GlobalFoundries 8RF-DM process. Here, the 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2026

Evaluation of an event-driven 3FI ASIC for spectroscopic X-ray detection with synchrotron radiation

The novel design and evaluation on the NSLS-II beamline of the 3FI application-specific integrated circuit (ASIC) bump-bonded to a simple, planar, 2D segmented silicon sensor are presented. The ASIC was developed for full-field fluorescence spectral X-ray imaging (3FI). It is a small-scale prototype that features a square array of 32 × 32 pixels, and the size of the pixels is 100 µm × 100 µm. The ASIC was implemented in a 65 nm CMOS integrated circuit fabrication process. Each pixel incorporates a charge-sensitive amplifier, a shaping filter, a discriminator, a peak detector and a sample-and-hold circuit, allowing detection of events and storage of signal amplitudes. The system operates in a frameless event-driven readout mode, outputting analog values for threshold-triggered events, allowing high-speed multi-element X-ray fluorescence data acquisition. The 3FI ASIC achieves per-channel spectrometric performance at a power consumption of only 200 µW per pixel, with nearly all dissipation confined to the analog front-end. An energy resolution is measured at the level of 308 eV full width at half-maximum (FWHM) at 8.04 keV (Cu Kα), and 138 eV FWHM at 3.69 keV (Ca Kα). This per-pixel capability makes the prototype suitable for in situ trace element microanalysis in biological and environmental studies. Moreover, the frameless architecture of the detector is designed to address limitations of conventional X-ray fluorescence microscopy, which typically requires mechanical scanning, by enabling continuous high-throughput data acquisition in future full-field implementations.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Electronics for the far-forward CMS muon detector upgrade, ME0

Abstract With the High Luminosity upgrade of the Large Hadron Collider (LHC) we expect increased instantaneous luminosities up to 7.5 × 10 34 cm −2 s −1 , or five times more than the original values. In order to maintain performance of the Compact Muon Solenoid (CMS) experiment under these conditions, ME0 is one of three new muon sub-detectors being added, along with GE1/1 and GE2/1, which use the triple Gas Electron Multiplier (GEM) technology. ME0 is designed to cover the forward region of 2.0 < | η | < 2.8, thus improving muon reconstruction at high background rates by supplementing other overlapping muon subsystems up to | η | = 2.4, while also extending the acceptance for the first time to | η | = 2.8. The readout electronics for ME0 must be designed to accommodate high data rates and be sufficiently radiation hard to operate close to the beamline. The Optohybrid (OH) board for ME0, which reads out data from the front-end VFAT3b ASICs, has therefore been designed to operate without an FPGA (unlike GE1/1 and GE2/1) to ensure radiation hardness. The ME0 OH uses the radiation-hard CERN-designed lpGBT ASIC and VTRx+ optical transceiver module for high bandwidth optical links up to 10.24 Gb/s. The backend system is based on the ATCA standard. The design and development status of the readout electronics for ME0 is presented, along with recent results from integration tests performed using the first prototypes.

Instruments & Instrumentation↗
DOE OSTI2020

Strip sensor performance in prototype modules built for ATLAS ITk

ATLAS experiment is preparing an upgrade of its detector for High-Luminosity LHC (HL-LHC) operation. The upgrade involves installation of the new all-silicon Inner Tracker (ITk). In the context of the ITk preparations, more than 80 strip modules were built with prototype barrel sensors. They were tested with electrical readout on a per-channel basis. In general, an excellent performance was observed, consistent with previous ASIC-level and sensor-level tests. However, the lessons learned included two phenomena important for the future phases of the project. First was the need to store and test the modules in a dry environment due to humidity sensitivity of the sensors. The second was an observation of high noise regions for 2 modules. The high noise regions were tested further in several ways, including monitoring the performance as a function of time and bias voltage. Additionally, direct sensor-level tests were performed on the affected channels. The inter-strip resistance and bias resistance tests showed low values, indicating a temporary loss of the inter-strip isolation. A subsequent recovery of the noise performance was observed. Here we present the test details, an analysis of how the inter-strip isolation affects the module noise, and the relationship with sensor-level quality control tests.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Design of a Time-to-Digital Converter ASIC and a mini-DAQ system for the Phase-2 upgrade of the ATLAS Monitored Drift Tube detector

We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been implemented for the configuration and flow control logic. Here, the total power consumption is increased by less than 10 mW while achieving the same time resolution and channel uniformity. A mini-DAQ system has been built to verify the front-end electronics chain with the new prototype together with other ASICs and boards in triggered mode. Cosmic ray tests with a small-diameter MDT chamber indicate that the configuration and data transmission of the readout electronics perform well. It is expected that this prototype design will be used in the final production.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Time-stamping and counting of single photons using fast camera

I will discuss fast optical cameras based on the back-illuminated silicon sensor and Timepix3 ASIC. The sensor has high quantum efficiency, and the chip provides nanosecond scale time resolution and data-driven readout with 80Mpix/sec bandwidth. The intensified version of the camera is single photon sensitive and since recently has been used for registration of single photons in a variety of quantum information science and quantum imaging experiments as well as for other applications. We briefly review the camera and describe recent experiments with a Hong-Ou-Mandel interferometer to characterize its photon counting capabilities.

79 ASTRONOMY AND ASTROPHYSICS↗
NASA NTRS2009

On DESTINY Science Instrument Electrical and Electronics Subsystem Framework

Future space missions are going to require large focal planes with many sensing arrays and hundreds of millions of pixels all read out at high data rates'' . This will place unique demands on the electrical and electronics (EE) subsystem design and it will be critically important to have high technology readiness level (TRL) EE concepts ready to support such missions. One such omission is the Joint Dark Energy Mission (JDEM) charged with making precise measurements of the expansion rate of the universe to reveal vital clues about the nature of dark energy - a hypothetical form of energy that permeates all of space and tends to increase the rate of the expansion. One of three JDEM concept studies - the Dark Energy Space Telescope (DESTINY) was conducted in 2008 at the NASA's Goddard Space Flight Center (GSFC) in Greenbelt, Maryland. This paper presents the EE subsystem framework, which evolved from the DESTINY science instrument study. It describes the main challenges and implementation concepts related to the design of an EE subsystem featuring multiple focal planes populated with dozens of large arrays and millions of pixels. The focal planes are passively cooled to cryogenic temperatures (below 140 K). The sensor mosaic is controlled by a large number of Readout Integrated Circuits and Application Specific Integrated Circuits - the ROICs/ASICs in near proximity to their sensor focal planes. The ASICs, in turn, are serviced by a set of "warm" EE subsystem boxes performing Field Programmable Gate Array (FPGA) based digital signal processing (DSP) computations of complex algorithms, such as sampling-up-the-ramp algorithm (SUTR), over large volumes of fast data streams. The SUTR boxes are supported by the Instrument Control/Command and Data Handling box (ICDH Primary and Backup boxes) for lossless data compression, command and low volume telemetry handling, power conversion and for communications with the spacecraft. The paper outlines how the JDEM DESTINY concept instrument EE subsystem can be built now, a design; which is generally U.S. Government work not protected by U.S. copyright IEEEAC paper # 1429. Version 4. Updated October 19, 2009 applicable to a wide variety of missions using large focal planes with lar ge mosaics of sensors.

Kizhner, Semion↗
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

From ETROC to VTROC

The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit, to reach 30-35ps per track with two detector layers. The ETROC2 is the first full size (16x16) prototype design and is fully compatible with the final chip specifications in terms of functionality. The ETROC2 has been extensively tested recently. In this talk, the testing results of the ETROC2 will be presented first, including performance study using charge injection, laser and beam, as well as TID testing and wafer probe testing to study the yield. In addition, future challenges of precision position and timing ASIC design will be discussed, based on what we have learned from the ETROC development, and how the challenges could be addressed in the VTROC, Vertically integrated Timing ReadOut chip (funded as SBIR phase 2) for precision position and timing detector R&D.

Liu, Ted↗
DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2025

The STAR Forward Silicon Tracker

The Forward Silicon Tracker (FST) is a pivotal component of the forward upgrade of the Solenoidal Tracker at RHIC (STAR), designed to discern hadron charge signs with a momentum resolution better than 30% for 0.2 < p T < 2GeV/c in the 2.5 < η < 4 pseudorapidity range. Its compact design features three disks along the beam direction, minimized material budget, and scattering effects. The FST uses Hamamatsu’s p-in-n silicon strip sensors with a double metal layer that enables efficient signal routing to the readout electronics, enhancing overall detector performance. The flexible hybrid boards, essential for the readout system, are constructed with Kapton and copper layers to optimize signal handling and power distribution. These boards connect silicon strips to analogue pipeline ASIC APV25-S1 chips, which read up to 128 channels each. A cooling system with nonconducting, volatile NOVEC 7200 coolant at 22.2 °C mitigates ASIC-generated heat. Furthermore, the FST enhances forward tracking performance at STAR as an integral part of the forward upgrade.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2025

MaPSA Quality Control and AI-Enhanced Grading For the CMS Phase-II Tracker Upgrade

The Compact Muon Solenoid (CMS) experiment will undergo changes as part of the Large Hadron Collider upgrade. The CMS tracker will be upgraded to cope with the new radiation environment and to provide tracking at the first level trigger. This upgrade features a new type of silicon module called PS Module, which combines a Pixel sensor and a Strip sensor in the same module. The pixel portion of the PS module has a sensor bump bonded to 16 Macro Pixel ASICs (MPA) to form a Macro Pixel Sub Assembly (MaPSA). At Fermilab, MaPSAs are tested for quality control before being assembled with the strip sensors, readout and service electronics to form a PS Module. All of this test data is stored in a centralized database, and is used to grade the final module to determine if it will be installed in the detector. The Phase II Outer Tracker Analyzer of Test Outputs (POTATO) is the software that processes this data and determines the module grades. Using recent technologies, an AI agent is being im plemented into POTATO in order to allow users to more efficiently sort through the large amounts of analysis data and ensure that only the user specified data is being considered. This poster will display the process of testing a MaPSA, how that test data is relevant to module assembly and grading, and how the POTATO grading tool is being improved with the use of an embedded AI agent.

Gzamouranis, Olivia [Purdue U.]↗
DOE OSTI2022

Beam test performance of a prototype module with Short Strip ASICs for the CMS HL-LHC tracker upgrade

The Short Strip ASIC (SSA) is one of the four front-end chips designed for the upgrade of the CMS Outer Tracker for the High Luminosity LHC. Together with the Macro-Pixel ASIC (MPA) it will instrument modules containing a strip and a macro-pixel sensor stacked on top of each other. The SSA provides both full readout of the strip hit information when triggered, and, together with the MPA, correlated clusters called stubs from the two sensors for use by the CMS Level-1 (L1) trigger system. Results from the first prototype module consisting of a sensor and two SSA chips are presented. The prototype module has been characterized at the Fermilab Test Beam Facility using a 120 GeV proton beam.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2016

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally approx.300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

data acquisition↗