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Noise variance maximum likelihood estimate based on order statistics for first order Reed-Muller code transmission over zero-mean white Gaussian noise channel
A decoding procedure is described for the (n,k) t-error-correcting Reed-Solomon (RS) code, and an implementation of the (31,15) RS code for the I4-TENEX central system. This code can be used for error correction in large archival memory systems. The principal features of the decoder are a Galois field arithmetic unit implemented by microprogramming a microprocessor, and syndrome calculation by using the g(x) encoding shift register. Complete decoding of the (31,15) code is expected to take less than 500 microsecs. The syndrome calculation is performed by hardware using the encoding shift register and a modified Chien search. The error location polynomial is computed by using Lin's table, which is an interpretation of Berlekamp's iterative algorithm. The error location numbers are calculated by using the Chien search. Finally, the error values are computed by using Forney's method.
This paper describes the encoding and the decoding of a (31,15) Reed-Solomon Code for multiple-burst error correction for large memory systems. The decoding procedure consists of four steps: (1) syndrome calculation, (2) error-location polynomial calculation, (3) error-location numbers calculation, and (4) error values calculation. The principal features of the design are the use of a hardware shift register for both high-speed encoding and syndrome calculation, and the use of a commercially available (31,15) decoder for decoding Steps 2, 3 and 4.
Analytical and experimental results are presented of the effects of receiver tracking phase error, caused by weak signal conditions on either the uplink or the downlink or both, on the performance of the concatenated Reed-Solomon (RS) Viterbi channel coding system. The test results were obtained under an emulated S band uplink and X band downlink, two way space communication channel in the telecommunication development laboratory of JPL with data rates ranging from 4 kHz to 20 kHz. It is shown that, with ideal interleaving, the concatenated RS/Viterbi coding system is capable of yielding large coding gains at very low bit error probabilities over the Viterbi decoded convolutional only coding system. Results on the effects of receiver tracking phase errors on the performance of the concatenated coding system with antenna array combining are included.
The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.
The use of Reed-Solomon (RS) block codes over the pulse position modulated (PPM) frames to obtain the largest degree of error correction is considered. Since RS codes can correct both symbol errors and symbol erasures, a question arises as to the best way to demodulate the PPM laser fields in order to generate the input symbols for the RS decoder. The method selected for demodulating (converting the received laser field to digital symbols) defines the erasure and transmitted symbols of the laser link, and therefore determines the work error probabilities of the system. Several demodulating schemes are considered, and the effect of each on RS decoding performance computed. This computation was carried out for various optical receiver models. It is shown that simple threshold decisioning of pulse slots produces performance that degrades as the background noise increases. This is caused by the generation of too many erasures for the RS decoder to handle. A decision scheme, delta-max demodulation which offers improvement over threshold decisioning by redefining the generation of an erasure is proposed.
In connection with attempts to achieve very low error probabilities, Odenwalder (1970) proposed a concatenated coding system using the Viterbi-decoded convolutional codes as the inner code and Reed-Solomon (RS) codes as the outer code. Analytical and experimental results are presented concerning the effects of the receiver tracking phase error on the performance of the concatenated RS/Viterbi channel coding system. On the basis of these results it is concluded that certain problems regarding communication operations on deep-space missions can be alleviated by employing the RS/Viterbi coding system. In one-way communication, an employment of RS/Viterbi coding will also provide greater data protection than the Viterbi-decoded convolutional-only coding system.
A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.
The Viterbi decoders currently used by the Deep Space Network (DSN) employ an algorithm for maintaining node synchronization that significantly degrades at bit signal-to-noise ratios (SNRs) of below 2.0 dB. In a recent report by the authors, it was shown that the telemetry receiving system, which uses a convolutionally encoded downlink, will suffer losses of 0.85 dB and 1.25 dB respectively at Voyager 2 Uranus and Neptune encounters. This report extends the results of that study to a concatenated (255,223) Reed-Solomon/(7, 1/2) convolutionally coded channel, by developing a new radio loss model for the concatenated channel. It is shown here that losses due to improper node synchronization of 0.57 dB at Uranus and 1.0 dB at Neptune can be expected if concatenated coding is used along with an array of one 64-meter and three 34-meter antennas.
The concatenated Reed-Solomon (RS)/Viterbi coding system is reviewed. The performance of the system is analyzed and results are derived with a new simple approach. A functional model for the input RS symbol error probability is presented. Based on this new functional model, we compute the performance of a concatenated system in terms of RS word error probability, output RS symbol error probability, bit error probability due to decoding failure, and bit error probability due to decoding error. Finally we analyze the effects of the noisy carrier reference and the slow fading on the system performance.
Concatenated coding was adopted for interplanetary space missions. Concatenated coding was employed with a convolutional inner code and a Reed-Solomon (RS) outer code for spacecraft telemetry. Conventional RS encoders are compared with those that incorporate two architectural features which approximately halve the number of multiplications of a set of fixed arguments by any RS codeword symbol. The fixed arguments and the RS symbols are taken from a nonbinary finite field. Each set of multiplications is bit-serially performed and completed during one (bit-serial) symbol shift. All firmware employed by conventional RS encoders is eliminated.
Design and operation of Reed-Solomon (RS) encoders discussed in document prepared as instruction manual for computer designers and others in dataprocessing field. Conventional and Berlekamp architectures compared. Engineers who equip computer memory chips with burst-error and dropout detection and correction find report especially useful.
Theory of Reed-Solomon codes yields sequences of input test symbols. Two specific sequences worked out for codes of 8 bits per symbol with 223 information symbols and 32 parity check symbols per code words. Test patterns also used for decoders.
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.
The paper proposes a delta-max demodulator for Reed-Solomon coded M-ary PPM modulation over optical (laser) channels including satellite-to-satellite and deep-space-vehicle-to-relay-satellite communications. This demodulator is compared with the threshold demodulator currently in use, and the two demodulators are shown to have identical performance in the absence of background noise. The delta-max demodulator is found to outperform the threshold demodulator as the intensity of background noise increases.
High-speed decoder intended for use with Reed-Solomon (RS) codes of long code length and high error-correcting capability. Design based on algorithm that includes high-radix Fermat transform procedure, which is most efficient for high speeds. RS code in question has code-word length of 256 symbols, of which 224 are information symbols and 32 are redundant.
Proposed Reed-Solomon (RS) decoder assembled from very-large-scale integrated-circuit (VLSI) building blocks. Decoder exploits recursive forms in RS decoding algorithms. RS codes capable of correcting random or burst errors in telemetry and other data-communication signals. Because of small size and low power consumption, advantageous to employ several such decoders in parallel-processing scheme to increase decoding speed.