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Parameter regions for proper operation of multifilter phase-lock loops used for demodulation are determined utilizing digital and analog computers. Experimental models are used to study these regions of proper operation. Generalized state models are developed for the multifilter phase-lock loop.
Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.
A new generation of multi-stage pi/4-shifted QPSK and of superposed quadrature-amplitude-modulated (SQAM) modulators-coherent demodulators (modems) and of continuous phase modulated (CPM)-gaussian premodulation filtered minimum-shift-keying (MGMSK) systems is proposed and studied. These modems will lead to bandwidth and power efficient satellite communications systems designs. As an illustrative application, a baseband processing technique pi/4-controlled transition PSK (pi/4-CTPSK) is described. To develop a cost and power efficient design strategy, we assume that nonlinear, fully saturated high power amplifiers (HPA) are utilized in the satellite earth station transmitter and in the satellite transponder. Modem structures which could lead to application specific integrated circuit (ASIC) satellite on-board processing universal modem applications are also considered. Multistate GMSK (i.e., MGMSK) signal generation methods by means of two or more RF combined nonlinearly amplified SQAM modems and by one multistate (in-phase and quadrature-baseband premodulation filtered-superposed) SQAM architecture and one RF nonlinear amplifier are studied. During the SQAM modem development phase we investigate the potential system advantages of the pi/4-shifted logic. The bandwidth efficiency of the proposed multistate GMSK and baseband filtered PAM-FM modulator (a new class in the CPM family) will be significantly higher than that of conventional G-MSK systems. To optimize the practical P(sub e) = f((E sub b)/(N sub o)) performance we consider improved coherent demodulation MGMSK structures such as deviated-frequency locking coherent demodulators. For relative low bit rate SATCOM applications, e.g., bit rates less than 300 kb/s, phase noise tracking cancellation (for fixed site earth station) and phase noise cancellation as well as Doppler compensation (for satellite to mobile earth station) applications may be required. We study digital channel sounding methods which could cancel the phase noise-caused degradations of CPM and GMSK modems.
Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.
Extended Kalman filter algorithms are used to obtain a digital phase lock loop structure for demodulation of angle modulated signals. It is shown that the error variance equations obtained directly from this structure enable one to predict threshold if one retains higher frequency terms. This is in sharp contrast to the similar analysis of the analog phase lock loop, where the higher frequency terms are filtered out because of the low pass filter in the loop. Results are compared to actual simulation results and threshold region results obtained previously.
Angle modulated carrier acquisition and demodulation, developing baseband model for behavior of output signal from phase lock loop
A bit synchronizer is analyzed via timing diagrams in a noise-free environment. It is believed that this new bit synchronizer will track the rising edge of the data bits with 25% asymmetry and up to a 90 deg phase shift between the received clock and data bit timing. In addition, the data bits will be demodulated correctly. It is not true that phase shifts larger than 90 deg will necessarily be corrected by this bit synchronizer. However, the specifications currently require the loop to operate over only a + or - 75 deg phase shift between the received data stream leading edges and the bit synchronizer leading edges; consequently, there should be no problem.
Suppressed carrier binary phase-shift keyed (BPSK) signalling is currently being considered as a design alternative for future DSN telemetry in the multimegabit range. Carrier tracking of such signals is usually achieved by a Costas loop, as opposed to the ordinary phase lock loop. A Costas loop capable of demodulating BPSK signals with data rates up to 1 Msps was designed and constructed and its Doppler tracking performance with respect to a Block 3 receiver was tested at the Telecommunications Development Laboratory (TDL). The compatibility of suppressed carrier signalling with the current radiometric system, specifically Doppler tracking and ranging, was investigated. The experimental results obtained to-date with respect to Doppler tracking are presented.
The feasibility for implementation of a concept for direct ac/dc multikilowatt power conversion with bidirectional transfer of energy was investigated. A 10 kHz current carrier was derived directly from a common 60 Hz three phase power system. This carrier was modulated to remove the 360 Hz ripple, inherent in the three phase power supply and then demodulated and processed by a high frequency filter. The resulting dc power was then supplied to a load. The process was implemented without the use of low frequency transformers and filters. This power conversion processes was reversible and can operate in the four quadrants as viewed from any of the two of the converter's ports. Areas of application include: power systems on air and spacecraft; terrestrial traction; integration of solar and wind powered systems with utility networks; HVDC; asynchronous coupling of polyphase networks; heat treatment; industrial machine drives; and power supplies for any use including instrumentation.
The subcarrier demodulation digital loop is part of the baseband assembly. The subcarrier demodulator is a fourth-order Costas-type loop corresponding to a type 2 analog loop in terms of steady state response. The expected value and the variance of the error signal are determined as functions of the input SNR. A Nyquist sampling rate of the input signal is assumed. From the integro-difference equations a mixed s/z domain block diagram is obtained. From the loop's transfer function a set of gains for the loop filter is obtained. Also, a set of state equations is presented for future reference. Finally, the noise-equivalent bandwidths are calculated for normalized computation times of 0, 0.25 and 0.5. The subcarrier demodulator analyzed tracks a parabolic phase input with finite steady state error. Since at each update instant the loop gains are adjusted to compensate for the variations in SNR of the input signal, the noise-equivalent bandwidth is maintained constant.
A newly developed two-way time synchronization system is described in this paper. The system uses one voice channel at a SCPC satellite digital communication earth station, whose bandwidth is only 45 kHz, thus saving satellite resources greatly. The system is composed of one master station and one or several, up to sixty-two, secondary stations. The master and secondary stations are equipped with the same equipment, including a set of timing equipment, a synthetic data terminal for time synchronizing, and a interface unit between the data terminal and the satellite earth station. The synthetic data terminal for time synchronization also has an IRIG-B code generator and a translator. The data terminal of master station is the key part of whole system. The system synchronization process is full automatic, which is controlled by the master station. Employing an autoscanning technique and conversational mode, the system accomplishes the following tasks: linking up liaison with each secondary station in turn, establishing a coarse time synchronization, calibrating date (years, months, days) and time of day (hours, minutes, seconds), precisely measuring the time difference between local station and the opposite station, exchanging measurement data, statistically processing the data, rejecting error terms, printing the data, calculating the clock difference and correcting the phase, thus realizing real-time synchronization from one point to multiple points. We also designed an adaptive phase circuit to eliminate the phase ambiguity of the PSK demodulator. The experiments have shown that the time synchronization accuracy is better than 2 mu S. The system has been put into regular operation.
Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.
Signal is demodulated and synchronized by three loop circuits: ''Q'' loop uses quadrature signal to stabilize frequency; ''B'' loop acts on baseboard signal to stabilize phase; and decoding ''I'' loop acts on in-phase signal. Synchronizer may be used to eliminate false-lock.
A bandwidth-efficient constant-envelope Proof-of-Concept (POC) modem is described. The modem was developed on an Advanced Modulation Techniques Development contract for the NASA/Lewis Research Center. The POC modem employs 16-ary Continuous Phase Frequency Shift Keying (16-CPFSK) modulation. The 16 frequencies are spaced every 1/16th baud rate which produces a compact spectrum allowing 2 bits/sec/Hz operation. The modem is designed for 200 mb/s Time Division Multiple Access (TDMA) application with 100 MHz adjacent channel spacing. Overall rate 3.4 convolutional coding is incorporated. The demodulator differs significantly from typical quadrature phase detector approaches in that phase is coherently measured by processing the baseband output of a frequency discriminator. Baud rate phase samples for the baseband processor are subsequently decoded to yield the original data stream. The method of encoding onto the 16-ary symbol-ending phase nodes, together with convolutional coding gain, results in near Quadrature Phase Shift Keying (QPSK) theoretical performance. The modulated signal is of constant envelope; thus the power amplifier can be saturated for peak performance. The spectrum is inherently bandlimited and requires no RF filter for sidelobe containment. Two novel theoretical techniques are used in this 16-CPFSK modem: (1) coherent phase measurements are obtained by processing an FM discriminator baseband output; and (2) modulation is accomplished via a closed-loop-linearized voltage controlled oscillator (VCO).
A digital demodulator for converting pulse code modulated data from phase shift key (PSK) to non return to zero (NRZ) and to biphase data is described. The demodulator is composed of standard integrated logic circuits. The key to the demodulation function is a pair of cross coupled one shot multivibrators and which with a flip-flop produce the NRZ-L is all that is required, the circuitry is greatly simplified and the 2(v) times bit rate contraint can be removed from the carrier. A flip-flop, an OR gate, and AND gate and a binary counter generate the bit rate clock (BTCK) for the NRZ-L. The remainder of the circuitry is for converting the NRZ-L and BTCK into biphase data. The device was designed for use in the space shuttle bay environment measurements.
A reference frequency distribution system is disclosed for transmitting a reference frequency from a reference unit to a remote unit while keeping the reference frequency at the reference unit and the remote unit in phase. A fiber optic cable connects the reference unit to the remote unit. A frequency source at the reference unit produces a reference frequency having an adjustable phase. A fiber optic transmitter at the reference unit modulates a light beam with the reference frequency and transmits the light beam into the fiber optic cable. A 50/50 reflector at the remote unit reflects a first portion of the light beam from the reference unit back into the fiber optic cable to the reference unit. A first fiber optic receiver disposed at the remote unit receives a second portion of the light beam and demodulates the reference frequency to be used at the remote unit. A second fiber optic receiver disposed at the reference unit receives the first portion of the light beam and demodulates a reference frequency component. A phase conjugator is connected to the frequency source for comparing the phase of the reference frequency component to the phase of the reference frequency modulating the light beam being transmitted from the reference unit to maintain a conjugate (anti-symmetric) relationship between the reference frequency component and the reference frequency modulating the light beam where virtually no phase difference exists between the phase of the reference frequency component and the phase of the reference frequency modulating the light beam.
To design a demodulator applicable to mobile satellite communication systems using differential phase shift keying modulation, we have developed key technologies including an anti-Rician-fading demodulation scheme, an initial acquisition scheme, automatic gain control (AGC), automatic frequency control (AFC), and bit timing recovery (BTR). Using these technologies, we have developed one-chip digital signal processor (DSP) modem for mobile terminal, which is compact, of light weight, and of low power consumption. Results of performance test show that the developed DSP modem achieves good performance in terms of bit error ratio in mobile satellite communication environment, i.e., Rician fading channel. It is also shown that the initial acquisition scheme acquires received signal rapidly even if the carrier-to-noise power ratio (CNR) of the received signal is considerably low.
This paper outlines the development of a digital demodulator suitable for the non-coherent detection of various modulation formats including: Phase Shift Keying (PSK), Continuous Phase Frequency Shift Keying (CPFSK) and Frequency Modulation (FM). The demodulator design concept has been derived with a view towards a single integrated circuit (IC) implementation. Two detectors, one non-coherent and one differentially coherent, operate concurrently, providing data detection and automatic frequency control (AFC). Bit error rate results are provided which illustrate the receiver performance in white Gaussian noise.