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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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97 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Soft error-mitigating semiconductor design system and associated methods

A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.

Miryala, Sandeep↗
DOE OSTI2020

OpenACC unified programming environment for GPU and FPGA multi-hybrid acceleration

Attached accelerators have been frequently used in recent High Per- formance Computing (HPC) systems because of their high performance/power ratio. In particular, the Graphics Processing Unit (GPU) is the most popu- lar accelerator owing to its high peak FLOPS performance and high memory bandwidth supported by HBM2, etc. However, the performance of GPU depends highly on a large degree of SIMD parallelism and has difficulty sustaining a high performance on programs with frequent branch operations or a partially low degree of parallelism.By contrast, a Field Programmable Gate Array (FPGA) has received attention as a different type of accelerator than GPU as a fully reconfigurable processor fitting the target applications. The high performance of FPGA is mainly provided by a pipelined operation and optimized circuit suitable for any operation even with frequent conditional branches. We have been focusing on the flexibility of FPGA to compensate for the weakness of GPU. We believe that the coupling of GPU with FPGA can result in one of the most powerful accelerating platforms available.However, the program coding of GPU and FPGA coupling can be quite difficult for application users. Traditionally, CUDA by NVIDIA has been the most popular programming language with the largest share of GPUs used in HPC, whereas a hardware description language such as Verilog HDL has been used in FPGA programming. OpenCL coding has recently become available even on high-end FPGAs. Moreover, several recent studies have also enabled the OpenACC coding for use in FPGA. In this study, we provide a unified programming system based on OpenACC for a platform equipped with both GPU and FPGA aiming at the next-generation accelerated supercomputer framework. Our programming environment is called Multi-Hybrid OpenACC Translator (MHOAT), and in this paper, we describe the basic concept and prototype system of MHOAT based on an evaluation on the amount of coding required and the performance of a hybrid multi-device accelerated system.

Tsunashima, Ryuta↗
DOE OSTI2024

Soft error-mitigating semiconductor design system and associated methods

A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.

Miryala, Sandeep↗
DOE OSTI2026

Surrogate Neural Architecture Codesign Package (SNAC-Pack)

Neural architecture search (NAS) is a powerful approach for automating model design, but existing methods often optimize for accuracy alone or rely on proxy metrics such as bit operations (BOPs) that correlate poorly with hardware cost. This gap is particularly large for FPGA deployment, where cost is dominated by a multi-dimensional budget of lookup tables, DSPs, flip-flops, BRAM, and latency. We present the Surrogate Neural Architecture Codesign Package (SNAC-Pack), an open-source AutoML framework for hardware-aware neural architecture codesign and end-to-end FPGA deployment. SNAC-Pack runs a multi-objective global search with Optuna and NSGA-II, loading trials to a shared SQLite store that enables parallel workers across compute nodes. A hardware surrogate model outputs per-trial resource and latency estimates, avoiding the synthesis cost that would otherwise dominate the search loop. A local search stage then applies quantization-aware training (QAT) together with iterative magnitude pruning in a combined compression loop, after which the final model is synthesized to FPGA firmware via the hls4ml Python library. A YAML configuration and an optional agentic frontend let users run the pipeline on new datasets without modifying the framework. We demonstrate SNAC-Pack on jet classification at the Large Hadron Collider and superconducting qubit readout, discovering compact architectures that match or exceed strong baselines on the task metric while reducing FPGA resource utilization and, in the qubit readout case, reducing the design space exploration process from months of manual fine-tuning to hours of automated search.

Weitz, Jason [UC, San Diego]↗
DOE OSTI2021

DNTTD (Distributed Non-Negative Tensor Train Decomposition)

The era of exascale computing opens new venues for innovations and discoveries in many scientific, engineering, and commercial fields. However, with the exa flops also come the extra-large high-dimensional data generated by high performance computing. High-dimensional data is presented as multidimensional arrays, aka tensors. The presence of latent (not directly observable) structures in the tensor allows a unique representation and compression of the data by classical tensor factorization techniques. However, the classical tensor methods are not always stable or they can be exponential in their memory requirements, which makes them not suitable for high-dimensional tensors. Tensor train (TT) is a state-of-the-art tensor network introduced for factorization of high-dimensional tensors. TT transforms the initial high-dimensional tensor in a network of three-dimensional tensors that requires only a linear storage. Many real-world data, such as, density, temperature, population, probability, etc., are non-negative and for an easy interpretation, the algorithms preserving non-negativity are preferred. Here, we introduce a distributed non-negative tensor-train and demonstrate its scalability and the compression on synthetic and real world big datasets.

Bhattarai, Manish↗
DOE OSTI2020

Magnetic Imaging of Domain Walls in the Antiferromagnetic Topological Insulator MnBi 2 Te 4

The control of domain walls or spin textures is crucial for spintronic applications of antiferromagnets. Despite many efforts, it has been challenging to directly visualize antiferromagnetic domains or domain walls with nanoscale resolution, especially in magnetic field. Here, we report magnetic imaging of domain walls in several uniaxial antiferromagnets, the topological insulator MnBi 2 Te 4 family, using cryogenic magnetic force microscopy (MFM). Our MFM results reveal higher magnetic susceptibility inside the domain walls than in domains. Domain walls in these antiferromagnets form randomly with strong thermal and magnetic field dependence. Here, the direct visualization of these domain walls and domain structures in the magnetic field will not only facilitate the exploration of intrinsic topological phenomena in antiferromagnetic topological insulators but will also open a new path toward control and manipulation of domain walls or spin textures in functional antiferromagnets.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Understanding and Tuning Magnetism in Layered Ising‐Type Antiferromagnet FePSe 3 for Potential 2D Magnet

Abstract Recent developments in 2D magnetic materials have motivated the search for new van der Waals magnetic materials, especially Ising‐type magnets with strong magnetic anisotropy. Fe‐based M P X 3 ( M = transition metal, X = chalcogen) compounds such as FePS 3 and FePSe 3 both exhibit an Ising‐type magnetic order, but FePSe 3 receives much less attention compared to FePS 3 . This work focuses on establishing the strategy to engineer magnetic anisotropy and exchange interactions in this less‐explored compound. Through chalcogen and metal substitutions, the magnetic anisotropy is found to be immune against S substitution for Se whereas tunable only with heavy Mn substitution for Fe. In particular, Mn substitution leads to a continuous rotation of magnetic moments from the out‐of‐plane direction toward the in‐plane. Furthermore, the magnetic ordering temperature displays non‐monotonic doping dependence for both chalcogen and metal substitutions but due to different mechanisms. These findings provide deeper insight into the Ising‐type magnetism in this important van der Waals material, shedding light on the study of other Ising‐type magnetic systems as well as discovering novel 2D magnets for potential applications in spintronics.

2D magnet↗