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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Digital twin advanced distribution management systems (ADMS) and methods

Advanced Distribution Management Systems not generally optimize over the entire feeder because there are few high-fidelity distribution circuit models and real-time distribution-connected sensors are rare. The limited observability at the distribution level makes it difficult to globally optimize distribution operations and issue control setpoints to power systems equipment or Distributed Energy Resources (DER) to perform grid-support services. For example, setpoints can be issued to DER based on results from an optimization module that incorporates a static or time-series feeder simulation. Feeder simulation initial conditions are populated with photovoltaic (PV) and load forecasts, state estimation results, and/or digital twin measurements or state output. The real-time (RT) digital twin runs a model of the feeder to generate state estimation pseudo-measurements since there are limited live feeder measurements.

Johnson, Jay Tillay↗
DOE OSTI2024

The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit

We report a very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Quantum simulations of hadron dynamics in the Schwinger model using 112 qubits

Hadron wave packets are prepared and time evolved in the Schwinger model using 112 qubits of IBM’s 133-qubit Heron quantum computer ibm_torino. The initialization of the hadron wave packet is performed in two steps. First, the vacuum is prepared across the whole lattice using the recently developed SC-ADAPT-VQE algorithm and workflow. SC-ADAPT-VQE is then extended to the preparation of localized states, and used to establish a hadron wave packet on top of the vacuum. This is done by adaptively constructing low-depth circuits that maximize the overlap with an adiabatically prepared hadron wave packet. Due to the localized nature of the wavepacket, these circuits can be determined on a sequence of small lattices using classical computers, and then robustly scaled to prepare wave packets on large lattices for simulations using quantum computers. Time evolution is implemented with a second-order Trotterization. To reduce both the required qubit connectivity and circuit depth, an approximate quasilocal interaction is introduced. This approximation is made possible by the emergence of confinement at long distances, and converges exponentially with increasing distance of the interactions. Using multiple error-mitigation strategies, up to 14 Trotter steps of time evolution are performed, employing 13,858 two-qubit gates (with a CNOT depth of 370). The propagation of hadrons is clearly identified, with results that compare favorably with Matrix Product State simulations. Finally, prospects for a near-term quantum advantage in simulations of hadron scattering are discussed.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

A First Step Towards Quantum Simulating Jet Evolution in a Dense Medium

The fast development of quantum technologies over the last decades has offered a glimpse to a future where the quantum properties of multi particle systems might be more fully understood. In particular, quantum computing might prove crucial to explore many aspects of high energy physics unaccessible to classical methods. In this talk, we will describe how one can use digital quantum computers to study the evolution of QCD jets in quark gluons plasmas. We construct a quantum circuit to study single particle evolution in a dense QCD medium. Focusing on the jet quenching parameter $\hat{q}$, we present some early numerical results for a small quantum circuit. Future extensions of this strategy are also addressed.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2025

A DATA EFFICIENT SPARSE MODELING FRAMEWORK FOR POWER ESTIMATION IN WATER TREATMENT SENSING OPERATIONS

With increasing freshwater scarcity, advanced process design mechanisms such as Closed-Circuit Reverse Osmosis (CCRO) and Digital/Physical Twin systems are gaining traction in water treatment and reuse operations. While digital and physical twin models enable improved system insight and control, their development is often expensive and computationally intensive, requiring large volumes of synthetic or experimental data to characterize underlying process dynamics. This work introduces a sparse surrogate modeling framework to estimate power consumption from measured flow and pressure variables, along with their nonlinear polynomial and interaction expansions. To ensure model reliability and reduce overfitting, a two-stage pipeline is proposed. First, a dynamic data filtering algorithm is employed to remove uninformative observations and transient operational states. Second, a sparse penalized regression technique is applied to select a minimal set of parsimonious features. The proposed model achieves high sparsity, retaining only 7 out of 34 candidate features (≈79.41% sparsity) while delivering a root mean square error (RMSE) of 0.072 on the test dataset.

Mukherjee, Subrata [ORNL] (ORCID:0000000309930338)↗
DOE OSTI2023

A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust

The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system's performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work further.

do Amaral Custodio, Paulo Vitor↗
DOE OSTI2021

Success of digital adiabatic simulation with large Trotter step

The simulation of adiabatic evolution has deep connections with adiabatic quantum computation, the quantum approximate optimization algorithm, and adiabatic state preparation. Here we address the error analysis problem in quantum simulation of adiabatic process using Trotter formulas. Here we show that with additional conditions, the circuit depth can be linear in simulation time T. The improvement comes from the observation that the fidelity error here can't be estimated by the norm distance between evolution operators. This phenomenon is termed the robustness of discretization in digital adiabatic simulation. It can be explained in three steps, from analytical and numerical evidence: (1) The fidelity error should be estimated by applying adiabatic theorem on the effective Hamiltonian instead. (2) Because of the specialty of Riemann-Lebesgue lemma, most adiabatic process is naturally robust against discretization. (3) As the Trotter step gets larger, the spectral gap of effective Hamiltonian tends to close, which results in the failure of digital adiabatic simulation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

Digital quantum simulation of Floquet symmetry-protected topological phases

Quantum many-body systems away from equilibrium host a rich variety of exotic phenomena that are forbidden by equilibrium thermodynamics. A prominent example is that of discrete time crystals, in which time-translational symmetry is spontaneously broken in periodically driven systems. Pioneering experiments have observed signatures of time crystalline phases with trapped ions, solid-state spin systems, ultracold atoms and superconducting qubits. Here we report the observation of a distinct type of non-equilibrium state of matter, Floquet symmetry-protected topological phases, which are implemented through digital quantum simulation with an array of programmable superconducting qubits. We observe robust long-lived temporal correlations and subharmonic temporal response for the edge spins over up to 40 driving cycles using a circuit of depth exceeding 240 and acting on 26 qubits. We demonstrate that the subharmonic response is independent of the initial state, and experimentally map out a phase boundary between the Floquet symmetry-protected topological and thermal phases. Our results establish a versatile digital simulation approach to exploring exotic non-equilibrium phases of matter with current noisy intermediate-scale quantum processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Feedback lock-in: A versatile multi-terminal measurement system for electrical transport devices

Here, we present the design and implementation of a measurement system that enables parallel drive and detection of small currents and voltages at numerous electrical contacts to a multi-terminal electrical device. This system, which we term a feedback lock-in, combines digital control-loop feedback with software-defined lock-in measurements to dynamically source currents and measure small, pre-amplified potentials. The effective input impedance of each current/voltage probe can be set via software, permitting any given contact to behave as an open-circuit voltage lead or as a virtually grounded current source/sink. This enables programmatic switching of measurement configurations and permits measurement of currents at multiple drain contacts without the use of current preamplifiers. Our 32-channel implementation relies on commercially available digital input/output boards, home-built voltage preamplifiers, and custom open-source software. With our feedback lock-in, we demonstrate differential measurement sensitivity comparable to a widely used commercially available lock-in amplifier and perform efficient multi-terminal electrical transport measurements on twisted bilayer graphene and SrTiO 3 quantum point contacts. The feedback lock-in also enables a new style of measurement using multiple current probes, which we demonstrate on a ballistic graphene device.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

In-Pixel Readout IC with compact in-pixel ADC for Pixel detectors at HL LHC

The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.

Parpillon, Benjamin↗
DOE OSTI2026

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗
DOE OSTI2024

HunStat – a simple and low-cost potentiostat for analytical and educational purposes

We have developed a truly low-cost (15 USD), simple do-it-yourself (DIY) potentiostat with compact dimensions. The output potential range of this device is between ±1.65 V. The developed instrument takes advantage of a Seeeduino XIAO microcontroller equipped with 10 bit digital-to-analog (D/A) and 12 bit analog-to-digital (A/D) converters and supports various voltammetry techniques, including cyclic voltammetry (CV), differential pulse voltammetry (DPV), and chronoamperometry (CA). Interested users are provided with circuit diagrams, bill of materials, and design files. Additionally, software components are also provided free of charge, including an Arduino sketch and control software. The software enables easy manipulation of electrochemical parameters and visualization of results. The presented design introduces a simple and low-cost DIY potentiostat recommended for both analytical and educational purposes.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Spread Spectrum Time Domain Reflectometry (SSTDR) Digital Twin Simulation of Photovoltaic Systems for Fault Detection and Location

Utilizing spread spectrum time domain reflectometry (SSTDR) to detect, locate, and characterize faults in photovoltaic (PV) systems is examined in this paper. We present a method to obtain the model parameters that are needed to produce digital twin SSTDR responses for PV systems. The digital twin SSTDR responses could be used to predict faults within the PV systems. Here, the model parameters are the reflection and transmission coefficients at each impedance discontinuity in the PV system along with the propagation coefficients across each PV cable segment. We obtain model parameter by applying inverse modeling techniques to experimental SSTDR data associated with PV systems. Our model parameters can be used in any digital twin simulation method for modeling reflectometry in frequency-dependent and complex loads. For validation, we used the model parameters in a graph network simulation engine and adapted it to be used for SSTDR digital twin simulations in PV systems. We produced simulations for 0 to 10 PV modules connected in series. We also simulated SSTDR responses for open circuit disconnections in a PV setup containing 10 PV modules in series. Results show that all but one simulated disconnect locations match experimental disconnection locations of the same setup with an error of less than 5%.

14 SOLAR ENERGY↗
DOE OSTI2023

Intelligent Proppants for Hydraulic Fracture Diagnostics

This Phase 1 Report details our Phase 1 progress in proving the feasibility of a highly integrated, highly miniaturized sensor ball. The ball contains sensors, analog to digital converters, memory, a clock, and an acoustic communications module all integrated onto a single silicon chip. Phase 2 is to focus on the application specific integrated circuit (ASIC). Phase 1 piecewise proves the feasibility of this innovation by examining a few critical subsystems including the communications module and inertial sensor performance. Acoustic simulations of an acoustically active and traceable proppant are also performed and summarized in this report.

01 COAL, LIGNITE, AND PEAT↗
DOE OSTI2024

Synthesis of Correct Digital Controller Models from Specifications by Model Transformation (21-0320)

The design of high consequence controllers (in weapons systems, autonomy, etc.) that do what they are supposed to do is a significant challenge. Testing simply does not come close to meeting the requirements for assurance. Today circuit designers at Sandia (and elsewhere) typically capture the core behavior of their components using state models in tools such as STATEFLOW. They then check that their models meet certain requirements (e.g. “The system bus must not deadlock” or “both traffic lights at an intersection must not be green at the same time”) using tools called model checkers. If the model checker returns “yes” then the property is guaranteed to be satisfied by the model. However, there are several drawbacks to this industry practice: (1) there is a lot of detail to get right, this is particularly challenging when there are multiple components requiring complex coordination (2) any errors returned by the model checker have to be traced back through the design and fixed, necessitating rework, (3) there are severe scalability problems with this approach, particularly when dealing with concurrency. All this places high demands on the designers who now face not only an accelerated schedule but also controllers of increasing complexity. This report describes a new and fundamentally different approach to the construction of safety-critical digital controllers. Instead of directly constructing a complete model and then trying to verify it, the designer can start with an initial abstract (think “sketch”) model plus the requirements, from which a correct concrete model is automatically synthesized. There is no need for post-hoc verification of required functional properties. Having tool to carry this out will significantly impact the nation’s ability to ensure the safety of high-consequence digital systems. The approach has been implemented in a prototype tool, along with a suite of examples, including ones that reflect actual problems faced by designers. Our approach operates on a variant of Statecharts developed at Sandia called Qspecs. Statecharts are a widely used formalism for developing concurrent reactive systems, supporting scalability through allowing state models containing composite states, which are the serial or parallel composition of substates which can themselves contain statecharts. Statecharts enable an incremental style of development, in which states are progressively refined to incorporate greater detail in an incremental model of software development. Our approach formulates a set of constraints from the structure of the models and the requirements and propagates these constraints to a fixpoint. The solution to the constraints is an inductive invariant along with guards on the transitions. We also show how our approach extends to implementation refinement, decomposition, composition, and elaboration. We currently handle safety requirements written in LTL (Linear Temporal Logic)

42 ENGINEERING↗
DOE OSTI2026

Large-scale real-time signal processing in physics experiments: the ALICE TPC FPGA pipeline

For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.

Digital signal processing (DSP)↗
DOE OSTI2023

Experimental results from the characterization of a 32-channels mixed-signal processor for the GAPS experiment

This work describes the experimental results obtained from the characterization of a 32-channels readout ASIC that is the core of a module composed by 4 Lithium-drifted Silicon, Si(Li), detectors. The module is the building block of a tracker in an upcoming balloon experiment. The activity is carried out within the General AntiParticle Spectrometer (GAPS) international collaboration, whose objective is the indirect detection of dark matter through the detection of antiparticles present in cosmic rays at low energies. The balloon flight is foreseen in 2024 from the McMurdo station in Antarctica. The ASIC is designed in a 180 nm CMOS technology and has 32 low-noise analog readout channels featuring a dynamic compression of the signal, an 11-bit SAR ADC, and a digital back-end section responsible for channel setting and for sending digital information to the data acquisition system of the tracker. This work has a twofold goal: it intends on the one hand to verify the performance of the circuit, on the other to select at least 300 good samples to be used for the assembly of the GAPS Si(Li) tracker.

Riceputi, Elisa↗
DOE OSTI2025

Optimization-Based Data-Driven Approach for Detecting Fault Location in Power Systems

In grids with large penetration of converterinterfaced resources (CIRs), measurements of voltage, current, and line parameters can fluctuate significantly during fault conditions. These fluctuations, combined with complex network topologies and extensive system branching, make accurate fault location challenging. Faults, such as short circuits, can cause prolonged outages with serious socio-economic impacts, highlighting the need for rapid fault identification to minimize downtime. However, current fault detection methods—such as relays and digital fault recorders—often relay information too slowly, impeding swift corrective action. Given the limited availability of high-resolution phasor measurement units, this paper introduces an optimization-based observer to estimate fault locations, grid line parameters, and voltages using local CIR measurements. To preserve the confidentiality of CIRs and enhance estimation accuracy, this study uses a black-box model of CIRs. This bottom-up, event-driven approach can enhances protection and control systems through optimized and real-time fault detection. Simulation results show that the optimization-based data-driven observer can accurately detect fault locations and estimate grid states and parameters, providing valuable insights for utilities and operators in grid applications.

Subedi, Sunil [ORNL] (ORCID:000000034069090X)↗