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At least 1,063 records · Page 59

Method and circuit for shaping laser output pulses

The invention is a method and circuit for shaping laser pulses 17' in which a laser medium 12' in a laser resonator 10' that includes a Q-switch 14' and polarizer 13' which act in combination to control the loss of the resonator 10' and provide the laser output 17' representative of such loss. An optical diode 22' senses the level of the output pulse 17' and provides an output signal 23' that when amplified is used with a control voltage from a supply 29' provide a control signal 19' which is applied to Q-switch 14' to control the shape of the output pulse 17' by adjusting its length.

Barnes, Norman P.↗

Optoelectronic Infrastructure for Radio Frequency and Optical Phased Arrays

Optoelectronic integrated circuits offer radiation-hardened solutions for satellite systems in addition to improved size, weight, power, and bandwidth characteristics. ODIS, Inc., has developed optoelectronic integrated circuit technology for sensing and data transfer in phased arrays. The technology applies integrated components (lasers, amplifiers, modulators, detectors, and optical waveguide switches) to a radio frequency (RF) array with true time delay for beamsteering. Optical beamsteering is achieved by controlling the current in a two-dimensional (2D) array. In this project, ODIS integrated key components to produce common RF-optical aperture operation.

Cai, Jianhong↗

Model Predictive Control of A Matrix-Converter Based Solid State Transformer for Utility Grid Interaction

The matrix converter solid state transformer (MC-SST), formed from the back-to-back connection of two three-to-single-phase matrix converters, is studied for use in the interconnection of two ac grids. The matrix converter topology provides a light weight and low volume single-stage bidirectional ac-ac power conversion without the need for a dc link. Thus, the lifetime limitations of dc-bus storage capacitors are avoided. However, space vector modulation of this type of MC-SST requires to compute vectors for each of the two MCs, which must be carefully coordinated to avoid commutation failure. An additional controller is also required to control power exchange between the two ac grids. In this paper, model predictive control (MPC) is proposed for an MC-SST connecting two different ac power grids. The proposed MPC predicts the circuit variables based on the discrete model of MC-SST system and the cost function is formulated so that the optimal switch vector for the next sample period is selected, thereby generating the required grid currents for the SST. Simulation and experimental studies are carried out to demonstrate the effectiveness and simplicity of the proposed MPC for such MC-SST-based grid interfacing systems.

Xue, Yaosuo↗

Harnessing the Second-Order Metal−Insulator Transition for Neuromorphic Computing

Vanadium oxides are widely studied phase change materials for brain-inspired computing architectures. Systems like VO 2 and V 2 O 3 exhibit first-order metal−insulator transitions (MITs) with hysteresis and percolative switching, increasing stochasticity and device variability. Here, we focus on the less explored Magnéli phase V 4 O 7 , which undergoes a continuous, non-hysteretic, second-order MIT. This surprisingly enables highly reproducible volatile resistive switching in spiking-neuron-type devices. We synthesize V 4 O 7 films, characterize their structural and transport properties, and demonstrate voltage and current-driven threshold switching with electrothermal feedback. In a Pearson–Anson oscillator, V 4 O 7 devices produce stable, tunable spiking across 20–200 kHz, with consistent operation among multiple devices. We introduce a numerical analog leaky-integrate-and-fire (aLIF) model that captures waveform shapes and their dependence on load resistance, temperature, and voltage. Furthermore, these findings suggest that second-order MIT materials like V 4 O 7 are promising for deterministic, scalable spiking neuron arrays for neuromorphic computing.

V4O7↗

A dynamic system matching technique for improving the accuracy of MEMS gyroscopes

A classical MEMS gyro transforms angular rates into electrical values through Euler's equations of angular rotation. Production models of a MEMS gyroscope will have manufacturing errors in the coefficients of the differential equations. The output signal of a production gyroscope will be corrupted by noise, with a major component of the noise due to the manufacturing errors. As is the case of the components in an analog electronic circuit, one way of controlling the variability of a subsystem is to impose extremely tight control on the manufacturing process so that the coefficient values are within some specified bounds. This can be expensive and may even be impossible as is the case in certain applications of micro-electromechanical (MEMS) sensors. In a recent paper [2], the authors introduced a method for combining the measurements from several nominally equal MEMS gyroscopes using a technique based on a concept from electronic circuit design called dynamic element matching [1]. Because the method in this paper deals with systems rather than elements, it is called a dynamic system matching technique (DSMT). The DSMT generates a single output by randomly switching the outputs of several, nominally identical, MEMS gyros in and out of the switch output. This has the effect of 'spreading the spectrum' of the noise caused by the coefficient errors generated in the manufacture of the individual gyros. A filter can then be used to eliminate that part of the spread spectrum that is outside the pass band of the gyro. A heuristic analysis in that paper argues that the DSMT can be used to control the effects of the random coefficient variations. In a follow-on paper [4], a simulation of a DSMT indicated that the heuristics were consistent. In this paper, analytic expressions of the DSMT noise are developed which confirm that the earlier conclusions are valid. These expressions include the various DSMT design parameters and, therefore, can be used as design tools for DSMT systems.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Development of a breadboard design of a high-performance, high-reliability switching regulator

A comparison of two potential conversion methods, the series inverter and the inductive energy transfer (IET) conversion technique, is presented. The investigations showed that a characteristic of the series inverter circuit (high equalizing current values in each half cycle) could not be accomplished with available components, and the investigations continued with the IET circuit only. An IET circuit system was built with the use of computer-aided design in a 2, 4, and 8 stage configuration, and these stages were staggered 180, 90, and 45 degrees, respectively. All stages were pulsewidth modulated to regulate over an input voltage range from 200 to 400 volts dc at a regulated output voltage of 56 volts. The output power capability was 100 to 500 watts for the 2 and 8 stage configuration and 50 to 250 watts for the 4 stage configuration. Equal control of up to eight 45 degree staggered stages was accomplished through the use of a digital-to-analog control circuit. Equal power sharing of all stages was achieved through a new technique using an inductively coupled balancing circuit. Conclusions are listed.

Lindena, S. J.↗

Wide Range SET Pulse Measurement

A method for measuring a wide range of SET pulses is demonstrated. Use of dynamic logic, faster than ordinary CMOS, allows capture of short pulses. A weighted binning of SET lengths allows measurement of a wide range of pulse lengths with compact circuitry. A pulse-length-conservative pulse combiner tree routes SETs from combinational logic to the measurement circuit, allowing SET measurements in circuits that cannot easily be arranged in long chains. The method is applied to add-multiplex combinational logic, and to an array of NFET routing switches, at .35 micron. Pulses are captured in a chain of Domino Logic AND gates. Propagation through the chain is frozen on the trailing edge by dropping low the second "enable" input to the AND gates. Capacitive loading is increased in the latter stages to create an approximately logarithmic weighted binning, so that a broad range of pulse lengths can be captured with a 10 stage capture chain. Simulations show pulses can be captured which are 1/5th the length of those typically captured with leading edge triggered latch methods, and less than the length of those captured with a trailing edge latch method. After capture, the pulse pattern is transferred to an SEU protected shift register for readout. 64 instances of each of two types of logic are used as targets. One is a full adder with a 4 to 1 mux on its inputs. The other is a 4 x 4 NFET routing matrix. The outputs are passed through buffered XNOR comparators to identify pulses, which are merged in a buffered not-nand (OR) tree designed to avoid pulse absorption as much as possible. The output from each of the two test circuits are input into separate pulse measurement circuits. Test inputs were provided so that the circuit could be bench tested and calibrated. A third SET measurement circuit with no inputs was used to judge the contribution from direct hits on the measurement circuit. Heavy ions were used with an LET range from 12 to 176. At LET of 21 and below, the very small number of SETs were not significantly higher in the test over the control circuits. At higher LET the test circuit SETs are one or two orders of magnitude greater than for the control circuit. The NFET circuit produces more and slightly longer SETs as expected. But the differences do not appear to be significant enough to modify strategies now used to avoid capture of SETs in chips such as FPGAs. Complete data and graphs will be in the full paper / presentation. In the summary figure below left, NOCL is the reference circuit without any input, and number of stages triggered is plotted. Simulation at right shows the smallest pulse captured (stage 2) at about 300 ps. Our conclusion is that the method is promising, but that improvements in the merge network are desirable before applying in a deep submicron process

Shuler, Robert L.↗

Chapter 11.2: Inverters, Power Optimizers, and Microinverters

Inverters span a wide range of sizes, topologies, and connection voltages: from utility-scale megawatt inverters to string inverters. Switch-mode power conversion relies on high frequency chopping of DC signal to periodically charge and discharge energy storage elements, such as inductors and capacitors. Additional circuit components are required to address practical issues in inverters such as voltage ripple and harmonic distortion. Inverters are beginning to incorporate components with a bandgap above should be 3 eV, such as SiC and GaN. Photovoltaic (PV) modules respond dynamically to changing temperature and irradiation conditions. Thus, maximum DC power extraction requires periodic adjustment of the PV voltage and current operating point. An inverter's total efficiency is measured by the product of its conversion efficiency and the maximum-power-point tracking (MPPT) efficiency. This chapter lists the primary functions of inverters that include auxiliary capabilities, such as monitoring of DC and AC performance, and other error reporting.

14 SOLAR ENERGY↗

Digital logic for soft devices

Although soft devices (grippers, actuators, and elementary robots) are rapidly becoming an integral part of the broad field of robotics, autonomy for completely soft devices has only begun to be developed. Adaptation of conventional systems of control to soft devices requires hard valves and electronic controls. This paper describes completely soft pneumatic digital logic gates having a physical scale appropriate for use with current (macroscopic) soft actuators. Each digital logic gate utilizes a single bistable valve—the pneumatic equivalent of a Schmitt trigger—which relies on the snap-through instability of a hemispherical membrane to kink internal tubes and operates with binary high/low input and output pressures. Soft, pneumatic NOT, AND, and OR digital logic gates—which generate known pneumatic outputs as a function of one, or multiple, pneumatic inputs—allow fabrication of digital logic circuits for a set–reset latch, two-bit shift register, leading-edge detector, digital-to-analog converter (DAC), and toggle switch. The DAC and toggle switch, in turn, can control and power a soft actuator (demonstrated using a pneu-net gripper). We note ehese macroscale soft digital logic gates are scalable to high volumes of airflow, do not consume power at steady state, and can be reconfigured to achieve multiple functionalities from a single design (including configurations that receive inputs from the environment and from human users). This work represents a step toward a strategy to develop autonomous control—one not involving an electronic interface or hard components—for soft devices.

36 MATERIALS SCIENCE↗

Open Radiation Monitoring: Histogram Builder Module Design

The Open Radiation Monitoring Project seeks to develop and demonstrate a modular radiation detection architecture designed specifically for use in arms control treaty verification (ACTV) applications that will facilitate rapid development of trusted systems to meet the needs of potential future treaties. A modular architecture can be used to reduce more complex systems to a series of single purpose building blocks, thereby facilitating equipment inspection and in turn building trust in the equipment by all treaty parties. Furthermore, a modular architecture can be used to control data flow within the measurement system, reducing the risk of "hidden switches" and constraining the amount of sensitive information that could potentially be inadvertently leaked. This report details the first revision of a prototype circuit that will convert analog pulses directly into a histogrammed data set for further processing. The circuit was designed with both spectroscopy and multiplicity analysis in mind but can, in principle, be used to reduce any raw data stream into a histogram. The number of output channels is limited, and the histogram bin ranges are user configurable to allow for non-uniform and discontinuous bins, which makes it possible to restrict the information being passed down stream if desired. Pulse processing relies entirely on analog circuitry and non- programmable logic, which enables operation without the need for a central processor or other programmable control unit. The circuit remains untested under the Open Radiation Monitoring project due to the closure of the sponsoring program. However, further development and testing is scheduled to take place in support of a purpose-built trusted verification system development effort known as COGNIZANT, which demonstrates the potential benefit of developing a suite of modular trusted system components.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

The LSLE echocardiograph - Commercial hardware aboard Spacelab

The Life Sciences Laboratory Equipment Echocardiograph, a commercial 77020AC Ultrasound Imaging System modified to meet NASA's spacecraft standards, is described. The assembly consists of four models: display and control, scanner, scan converter, and physioamplifiers. Four separate processors communicate over an IEE-488 bus, and the system has more than 6000 individual components on 35 printed circuit cards. Three levels of self test are provided: a short test during power up, a basic test initiated by a front panel switch, and interactive tests for specific routines. Default mode operation further enhances reliability. Modifications of the original system include the replacement of ac power supplies with dc to dc converters, a slide-out keyboard (to prevent accidental operation), Teflon insulated wire, and additional shielding for the ultrasound transducer cable.

Schwarz, R.↗

Analysis of the 60-Hz power system at KSC: The Orsino substation

An analysis of the Orsino Substation, a component (50 percent) of the 60-Hertz electric power system at the Kennedy Space Center, is presented. Presented here are separate single-line diagrams of the sixteen feeder circuits to permit easy access to information on the individual feeders for future planning. The load condition of each feeder and load break switch are presented and a heuristic reliability analysis of the system is performed. Information is given about the system fashion useful for decision making purposes. The beauty of it is in the simplified manner by which information about the system can be obtained.

Kalu, Alex O.↗

Photonics

Optoelectronic materials and devices are examined. Optoelectronic devices, which generate, detect, modulate, or switch electromagnetic radiation are being developed for a variety of space applications. The program includes spatial light modulators, solid state lasers, optoelectronic integrated circuits, nonlinear optical materials and devices, fiber optics, and optical networking photovoltaic technology and optical processing.

Source record↗

Authentication, Time-Stamping and Digital Signatures

Time and frequency data are often transmitted over public packet-switched networks, and the use of this mode of distribution is likely to increase in the near future as high-speed logical circuits transmitted via networks replace point-to-point physical circuits. ALthough these networks have many technical advantages, they are susceptible to evesdropping, spoofing, and the alteration of messages enroute using techniques that are relatively simple to implement and quite difficult to detect. I will discuss a number of solutions to these problems, including the authentication mechanism used in the Network Time Protocol (NTP) and the more general technique of signing time-stamps using public key cryptography. This public key method can also be used to implement the digital analog of a Notary Public, and I will discuss how such a system could be realized on a public network such as the Internet.

Levine, Judah↗

Efficient Design in a DC to DC Converter Unit

Space Flight hardware requires high power conversion efficiencies due to limited power availability and weight penalties of cooling systems. The International Space Station (ISS) Electric Power System (EPS) DC-DC Converter Unit (DDCU) power converter is no exception. This paper explores the design methods and tradeoffs that were utilized to accomplish high efficiency in the DDCU. An isolating DC to DC converter was selected for the ISS power system because of requirements for separate primary and secondary grounds and for a well-regulated secondary output voltage derived from a widely varying input voltage. A flyback-current-fed push-pull topology or improved Weinberg circuit was chosen for this converter because of its potential for high efficiency and reliability. To enhance efficiency, a non-dissipative snubber circuit for the very-low-Rds-on Field Effect Transistors (FETs) was utilized, redistributing the energy that could be wasted during the switching cycle of the power FETs. A unique, low-impedance connection system was utilized to improve contact resistance over a bolted connection. For improved consistency in performance and to lower internal wiring inductance and losses a planar bus system is employed. All of these choices contributed to the design of a 6.25 KW regulated dc to dc converter that is 95 percent efficient. The methodology used in the design of this DC to DC Converter Unit may be directly applicable to other systems that require a conservative approach to efficient power conversion and distribution.

Bruemmer, Joel E.↗

Design of Timer Circuit for Dynamic Data System

The Branch That I work in is in the Aero Electronic Test Branch, which is part of the Research and Testing Division. The Aero Electronic Test Branch deals with electronic control and instrumentation systems. This branch supports the research and test study of wind tunnels such as the l0x10,9x15, and 8x6. Wind tunnels are used in research to test certain parts of a jet, plane, shuttle or any other flying object in certain test conditions. My assignment is to design a programmable trigger circuit on a 19 standard rack mount that will allow the circuit to latch and hold for a predefined amount of time entered by the user when receiving a signal. It should then re-arm itself within 0.25 seconds after the time is finished. The time should be able to be seen on a display showing the time entered. The time range has to be from 0-600 seconds in 0.01 second increments (600.00). From the information given, counters will be needed to design and build this circuit. A counter, in it s simplest form, is a group of flip flops that can temporarily store bits of information put into the circuit. They can be constructed in many different ways, such as in 4 flip flops (4-bit counter) or 8 flip flops and even higher. Counters are usually cascaded with other counters to reach higher bits, such as 16 or 24 bit counters. The application in which I will use the counters will be to count down from any programmable number that I input either by a keyboard or a thumbwheel. Also, I will use counters that will be used specifically as a frequency divider to divide the pulses that enter the circuit through an input signal from a crystal clock. The pulses will need to be divided so that it will function as a 100Hz clock putting out 100 pulses per second. A switch will be used to load my inputs in and more than likely a button also so that I can stop and hold the count at any point of time. I will use 5 BCD up/down programmable counters, and a certain amount (depending on what kind of "divide by N" counter I use) of frequency dividing counters for the assignment. After the design is carefully made, a task order will be written and then given to the manufacturer to create a rack mount circuit board that will match my specifications given. The applications in which this design will be used for is in the use of the six-component balance signal conditioner for measurement and electronic system control. It can be used as a timer system for the balance signal conditioner in which it does numerous tests for the Wind tunnel research, in which a preset time can be set for how long it performs its tests. Specifically, my design should be applied to the balance signal conditioner used for the 8x6 wind tunnel research. Hopefully this design should aid in more efficient research for the 8x6 wind tunnel.

Young, Nathaniel, III↗

Reversible conversion of dominant polarity in ambipolar polymer/graphene oxide hybrids

The possibility to selectively modulate the charge carrier transport in semiconducting materials is extremely challenging for the development of high performance and low-power consuming logic circuits. Systematical control over the polarity (electrons and holes) in transistor based on solution processed layer by layer polymer/graphene oxide hybrid system has been demonstrated. The conversion degree of the polarity is well controlled and reversible by trapping the opposite carriers. Basically, an electron device is switched to be a hole only device or vice versa. Finally, a hybrid layer ambipolar inverter is demonstrated in which almost no leakage of opposite carrier is found. We conclude that this hybrid material has wide range of applications in planar p-n junctions and logic circuits for high-throughput manufacturing of printed electronic circuits.

36 MATERIALS SCIENCE↗

Involvement of a chromatin modifier in response to mono-(2-ethylhexyl) phthalate (MEHP)-induced Sertoli cell injury: Probably an indirect action via the regulation of NFκB/FasL circuitry

Highlights: •MTA1 expression is upregulated in SCs upon MEHP treatment. •Knockdown of MTA1 in SCs impairs the MEHP-induced NFκB signaling activation. •Knockdown of MTA1 inhibits recruitment of NFκB onto FasL promoter in MEHP-treated SCs. -- Abstract: The Fas/FasL signaling pathway, controlled by nuclear factor-κB (NFκB) at the transcriptional level, is critical for triggering germ cell apoptosis in response to mono-(2-ethylhexyl) phthalate (MEHP)-induced Sertoli cell (SC) injury, but the exact regulation mechanism remain unknown. Here, we discovered that expression level of Metastasis associated protein 1 (MTA1), a component of the Mi-2/nucleosome remodeling and deacetylase complex, was upregulated in SCs during the early recovery after MEHP exposure. This expression change was in line with the dynamic changes in germ cell apoptosis in response to MEHP treatment. Furthermore, a knockdown of MTA1 by RNAi in SCs was found to impair the MEHP-induced early activation of NFκB pathway and abolish the recruitment of NFκB onto FasL promoter, which consequently diminished the MEHP-triggered FasL induction. Considering that Fas/FasL is a well characterized apoptosis initiating signaling during SCs injury, our results point to a potential “switch on” effect of MTA1, which may govern the activation of NFκB/FasL cascade in MEHP-insulted SCs. Overall, the MTA1/NFκB/FasL circuit may serve as an important defensive/repairing mechanism to help to control the germ cell quality after SCs injury.

60 APPLIED LIFE SCIENCES↗