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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,063 records · Page 59
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Low temperature plasma enhanced atomic layer deposition of conducting zirconium nitride films using tetrakis (dimethylamido) zirconium and forming gas (5% H{sub 2} + 95% N{sub 2}) plasma

Zirconium nitride (ZrN) has the lowest bulk electrical resistivity and high thermal stability among group IV and V transition metal nitrides, which makes it a promising material for ULSI applications such as a diffusion barrier for Cu interconnects, contact metal in III-V semiconductor devices, and in high density memory structures. Plasma enhanced atomic layer deposition (PEALD) of conducting ZrN thin films using Zr[N(CH{sub 3}){sub 2}]{sub 4} and forming gas (5% H{sub 2} + 95% N{sub 2}) plasma is reported in this article. The growth per cycle (GPC) for every deposition was determined from analysis of dynamic in-situ spectroscopic ellipsometry (d-iSE) measurements. An experimental design is proposed for faster determination of ALD growth saturation curves. At substrate temperature of 150 °C, a GPC of 0.10 nm/cycle was observed for self-limiting ZrN PEALD growth. The electrical resistivity of ZrN films deposited on SiO{sub 2} substrate was found to be 559.5 ± 18.5 μΩ cm with negligible change in resistivity even after ∼1000 h exposure to air. The metallic behavior of our ZrN films was evident from the free electron dispersion component in dielectric response, the broad band of photoelectron emission across Fermi level and the positive temperature coefficient for resistivity of 0.0088/ °C.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Revisiting Temporal Blocking Stencil Optimizations

Iterative stencils are used widely across the spectrum of High Performance Computing (HPC) applications. Many efforts have been put into optimizing stencil GPU kernels, given the prevalence of GPU-accelerated supercomputers. To improve the data locality, temporal blocking is an optimization that combines a batch of time steps to process them together. Under the observation that GPUs are evolving to resemble CPUs in some aspects, we revisit temporal blocking optimizations for GPUs. We explore how temporal blocking schemes can be adapted to the new features in the recent Nvidia GPUs, including large scratchpad memory, hardware prefetching, and device-wide synchronization. We propose a novel temporal blocking method, EBISU, which champions low device occupancy to drive aggressive deep temporal blocking on large tiles that are executed tile-by-tile. We compare EBISU with state-of-the-art temporal blocking libraries: STENCILGEN and AN5D. We also compare with state-of-the-art stencil auto-tuning tools that are equipped with temporal blocking optimizations: ARTEMIS and DRSTENCIL. Over a wide range of stencil benchmarks, EBISU achieves speedups up to 2.53x and a geometric mean speedup of 1.49x over the best state-of-the-art performance in each stencil benchmark.

Zhang, Lingqi↗
DOE OSTI2024

Strain-concentration for fast, compact photonic modulation and non-volatile memory

A critical figure of merit (FoM) for electro-optic (EO) modulators is the transmission change per voltage, d T / d V . Conventional approaches in wave-guided modulators maximize d T / d V via a high EO coefficient or longer light-material interaction lengths but are ultimately limited by material losses and nonlinearities. Optical and RF resonances improve d T / d V at the cost of spectral non-uniformity, especially for high- Q optical cavity resonances. Here, we introduce an EO modulator based on piezo-strain-concentration of a photonic crystal cavity to address both trade-offs: (i) it eliminates the trade-off between d T / d V and waveguide loss—i.e., enhancement of the resonance tuning efficiency d v c / d V for the fixed EO coefficient, waveguide length, and cavity Q —and (ii) at high DC strains it exhibits a non-volatile (NV) cavity tuning Δ v c ,NV for passive memory and programming of multiple devices into resonance despite fabrication variations. The device is fabricated on a scalable silicon nitride-on-aluminum nitride platform. We measure d v c / d V =177±1MHz/V, corresponding to Δ v c =40±0.32GHz for a voltage spanning ±120V with an energy consumption of δ U /Δ v c =0.17nW/GHz. The modulation bandwidth is flat up to ω BW,3dB /2 π =3.2±0.07MHz for broadband DC-AC and 142±17MHz for resonant operation near a 2.8 GHz mechanical resonance. Optical extinction up to 25 dB is obtained via Fano-type interference. Strain-induced beam-buckling modes are programmable under a “read-write” protocol with a continuous, repeatable tuning range of 5±0.25GHz, allowing for storage and retrieval, which we quantify with mutual information of 2.4 bits and a maximum non-volatile excursion of 8 GHz. Using a full piezo-optical finite-element-model (FEM) we identify key design principles for optimizing strain-based modulators and chart a path towards achieving performance comparable to lithium niobate-based modulators and the study of high strain physics on-chip.

Wen, Y. Henry (ORCID:0009000685423628)↗
DOE OSTI2017

Taguchi Design of Experiment Enabling the Reduction of Spikes on the Sides of Patterned Thin Films for Tunnel Junction Fabrication

Photolithographically patterned thin films often possess unwanted spikes along the side edges. These spikes are a significant issue for the development of spinvalve memory, tunnel junction based molecular devices, and micro-electromechanical systems. Here, we report a very simple, economical, and fast way of creating an optimum photoresist profile for the production of spike-free patterned films. This approach is based on performing a soaking step in the positive-photoresist’s developer solution before the UV exposure. However, the success of this method depends on multiple photolithography factors: photoresist thickness (governed by spin speed), soft baking temperature, soaking time in developer, and exposure time. In this paper, we report our systematic experiments to study the effect of these factors by following the L9 experimental scheme of the Taguchi Design of experiment (TDOE) approach. The L9 experiment scheme effectively accommodated the study of four photolithography factors, each with three levels. After performing photolithography as per L9 TDOE scheme, we sputter deposited 20 nm Tantalum to check the side edge profile of the patterned film by atomic force microscope (AFM). We measured the heights of the spikes along the thin film edges. We utilized spike height as the desired property and chose “smaller the better” criteria for the TDOE analysis. TDOE enabled us to understand the relative importance of the parameters, relationship among the parameters, and impact of the various levels of the parameters on the thin film edge profile. TDOE analysis yielded an optimum combination of levels for the four photolithography factors. The optimum combination of photolithography factors included spin speed 4000 rpm, 100 °C soft baking temperature, 60 sec pre-soaking in the developer solution, and 15 sec UV exposure. We validated the TDOE by AFM and observed spike free patterned films. Here, we also made complete tunnel junction devices by utilizing the optimized photolithography factors for the bottom electrode and obtained excellent tunneling behavior. In summary, this study provides a very simple, economical, and fast photolithography approach for creating optimum photoresist profile for the micro-nano scale devices and electromechanical structures.

36 MATERIALS SCIENCE↗
DOE OSTI2013

Hetero-junctions of Boron Nitride and Carbon Nanotubes: Synthesis and Characterization

Hetero-junctions of boron nitride nanotubes (BNNTs) and carbon nanotubes (CNTs) are expected to have appealing new properties that are not available from pure BNNTs and CNTs. Theoretical studies indicate that BNNT/CNT junctions could be multifunctional and applicable as memory, spintronic, electronic, and photonics devices with tunable band structures. This will lead to energy and material efficient multifunctional devices that will be beneficial to the society. However, experimental realization of BNNT/CNT junctions was hindered by the absent of a common growth technique for BNNTs and CNTs. In fact, the synthesis of BNNTs was very challenging and may involve high temperatures (up to 3000 degree Celsius by laser ablation) and explosive chemicals. During the award period, we have successfully developed a simple chemical vapor deposition (CVD) technique to grow BNNTs at 1100-1200 degree Celsius without using dangerous chemicals. A series of common catalyst have then been identified for the synthesis of BNNTs and CNTs. Both of these breakthroughs have led to our preliminary success in growing two types of BNNT/CNT junctions and two additional new nanostructures: 1) branching BNNT/CNT junctions and 2) co-axial BNNT/CNT junctions, 3) quantum dots functionalized BNNTs (QDs-BNNTs), 4) BNNT/graphene junctions. We have started to understand their structural, compositional, and electronic properties. Latest results indicate that the branching BNNT/CNT junctions and QDs-BNNTs are functional as room-temperature tunneling devices. We have submitted the application of a renewal grant to continue the study of these new energy efficient materials. Finally, this project has also strengthened our collaborations with multiple Department of Energy's Nanoscale Science Research Centers (NSRCs), including the Center for Nanophase Materials Sciences (CNMS) at Oak Ridge National Laboratory, and the Center for Integrated Nanotechnologies (CINTs) at Sandia National Laboratories and Los Alamos National Laboratory. Results obtained during the current funding period have led to the publication of twelve peer reviewed articles, three review papers, two book and one encyclopedia chapters, and thirty eight conference/seminar presentation. One US provisional patent and one international patent have also been filed.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Exploring transport-enabled gates with integrated optical addressing to demonstrate high fidelity control of trapped ion qubits in a scalable quantum computer

In recent years, experiments involving micofabricated surface ion traps have grown in complexity, and as this complexity grows, a common design has emerged in the form of quantum charge-coupled device architecture. This architecture, already utilized on multiple systems, supports multiple zones on a device for areas such as memory or computation. The shutting process between these zones is a process often seen to be minimized. An additional component to scalable surface trapped-ion experiments includes some form of integrated photonics, as free space lasers have difficulty scaling to many ions. Here, we discuss recent results in utilizing the shuttling process with integrated photonics to perform a specific type of gate, as well as demonstrating state preparation. Furthermore, we show that these gates can be utilized as a type of optical modulator as the Doppler shift that occurs during shuttling will make the light seen by shuttled ions different than that seen by stationary ions. Furthermore, we show that the shuttling operation can be utilized as an optical modulator, where the Doppler shift changes the frequency from that of a stationary ion.

42 ENGINEERING↗
NASA NTRS1985

Advances in rechargeable lithium molybdenum disulfide batteries

The lithium molybdenum disulfide system as demonstrated in a C size cell, offers performance characteristics for applications where light weight and low volume are important. A gravimetric energy density of 90 watt hours per kilogram can be achieved in a C size cell package. The combination of charge retention capabilities, high energy density and a state of charge indicator in a rechargeable cell provides power package for a wide range of devices. The system overcomes the memory effect in Nicads where the full capacity of the battery cannot be utilized unless it was utilized on previous cycles. The development of cells with an advanced electrolyte formulation led to an improved rate capability especially at low temperatures and to a significantly improved life cycle.

Brandt, K.↗
NASA NTRS1985

Computers in Aerospace Conference, 5th, Long Beach, CA, October 21-23, 1985, Technical Papers

Among the topics discussed are: access control models for a distributed CAIS-conforming system; a knowledge-based advisory system for casualty procedures; and automated interactive simulation modeling system. Consideration is also given to: reusable software concepts and software development methodologies; the electronic device aspects of neutral network memories; an expert system for automated satellite anomaly resolution; and the use of automatic programming techniques for fault-tolerant computing systems. Among additional topics discussed are: systems approaches to software fault tolerance; a Space Shuttle navigation validation system; and a vision-based road following system for an autonomous land vehicle.

Source record↗
NASA NTRS1990

Temperature Dependence Of Single-Event Effects

Report describes experimental study of effects of temperature on vulnerability of integrated-circuit memories and other electronic logic devices to single-event effects - spurious bit flips or latch-up in logic state caused by impacts of energetic ions. Involved analysis of data on 14 different device types. In most cases examined, vulnerability to these effects increased or remain constant with temperature.

Coss, James R.↗
NASA NTRS1992

Coupling device with improved thermal interface

The primary object of the present invention is to provide a simple, reliable, and lightweight coupling that will also have an efficient thermal interface. A further object of the invention is to provide a coupling that is capable of blind mating with little or no insertion forces. Another object of the invention is to provide a coupling that acts as a thermal regulator to maintain a constant temperature on one side of the coupling. Another object of the invention is to increase the available surface area of a coupling thus providing a larger area for the conduction of heat across the thermal interface. Another object of the invention is to provide a fluidic coupling that has no fluid passing across the interface, thus reducing the likelihood of leaks and contamination. The foregoing objects are achieved by utilizing, as in the prior art, a hot area (at an elevated temperature as compared to a cold area) with a need to remove excess heat from the hot area to a cold area. In this device, the thermal interface will occur not on a planar horizontal surface, but along a non-planar vertical surface, which will reduce the reaction forces and increase the thermal conductivity of the device. One non-planar surface is a surface on a cold pin extending from the cold area and the other non-planar surface is a surface on a hot pin extending from the hot area. The cold pin is fixed and does not move while the hot pin is a flexible member and its movement towards the cold pin will bring the two non-planar surfaces together forming the thermal interface. The actuating member for the device is a shape-memory actuation wire which is attached through an aperture to the hot pin and through another aperture to an actuation wire retainer. By properly programming the actuation wire, heat from the hot area will cause the actuation wire to bend the hot wire. Heat from the hot area will cause the actuation wire to bend the hot pin towards the cold pin forming the coupling and the desired thermal interface. The shape-memory actuation wire is made of a shape-memory-effect alloy such as Nitinol.

Milam, Malcolm Bruce↗
NASA NTRS2005

Reconfigurable Processing Module

To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to the moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Application FPGA - or simply "the application" - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

Somervill, Kevin↗
NASA NTRS2006

General Aviation Data Framework

The Flight Research Services Directorate at the NASA Langley Research Center (LaRC) provides development and operations services associated with three general aviation (GA) aircraft used for research experiments. The GA aircraft includes a Cessna 206X Stationair, a Lancair Colombia 300X, and a Cirrus SR22X. Since 2004, the GA Data Framework software was designed and implemented to gather data from a varying set of hardware and software sources as well as enable transfer of the data to other computers or devices. The key requirements for the GA Data Framework software include platform independence, the ability to reuse the framework for different projects without changing the framework code, graphics display capabilities, and the ability to vary the interfaces and their performance. Data received from the various devices is stored in shared memory. This paper concentrates on the object oriented software design patterns within the General Aviation Data Framework, and how they enable the construction of project specific software without changing the base classes. The issues of platform independence and multi-threading which enable interfaces to run at different frame rates are also discussed in this paper.

Blount, Elaine M.↗
NASA NTRS1998

Remotely controllable actuating device

An actuating device can change a position of an active member that remains in substantially the same position in the absence of a force of a predetermined magnitude on the active member. The actuating device comprises a shape-memory alloy actuating member for exerting a force when actuated by changing the temperature thereof, which shape-memory alloy actuating member has a portion for connection to the active member for exerting thereon a force having a magnitude at least as large as the predetermined magnitude for moving the active member to a desired position. Actuation circuitry is provided for actuating the shape-memory alloy actuating member by changing the temperature thereof only for the time necessary to move the active member to the desired position. The invention is particularly useful for changing the position of a camber-adjusting tab on a helicopter rotor blade by using two shape-memory alloy members that can act against each other to adjust dynamic properties of the rotor blade as it is rotating.

McKillip, Jr., Robert M.↗
NASA NTRS2012

Goldstone Solar System Radar Waveform Generator

Due to distances and relative motions among the transmitter, target object, and receiver, the time-base between any transmitted and received signal will undergo distortion. Pre-distortion of the transmitted signal to compensate for this time-base distortion allows reception of an undistorted signal. In most radar applications, an arbitrary waveform generator (AWG) would be used to store the pre-calculated waveform and then play back this waveform during transmission. The Goldstone Solar System Radar (GSSR), however, has transmission durations that exceed the available memory storage of such a device. A waveform generator capable of real-time pre-distortion of a radar waveform to a given time-base distortion function is needed. To pre-distort the transmitted signal, both the baseband radar waveform and the RF carrier must be modified. In the GSSR, this occurs at the up-conversion mixing stage to an intermediate frequency (IF). A programmable oscillator (PO) is used to generate the IF along with a time-varying phase component that matches the time-base distortion of the RF carrier. This serves as the IF input to the waveform generator where it is mixed with a baseband radar waveform whose time-base has been distorted to match the given time-base distortion function producing the modulated IF output. An error control feedback loop is used to precisely control the time-base distortion of the baseband waveform, allowing its real-time generation. The waveform generator produces IF modulated radar waveforms whose time-base has been pre-distorted to match a given arbitrary function. The following waveforms are supported: continuous wave (CW), frequency hopped (FH), binary phase code (BPC), and linear frequency modulation (LFM). The waveform generator takes as input an IF with a time varying phase component that matches the time-base distortion of the carrier. The waveform generator supports interconnection with deep-space network (DSN) timing and frequency standards, and is controlled through a 1 Gb/s Ethernet UDP/IP interface. This real-time generation of a timebase distorted radar waveform for continuous transmission in a planetary radar is a unique capability.

Quirk, Kevin J.↗
NASA NTRS2020

Avalanche ASV016204 (Pre-Production Samples) 40nm MRAM Total Ionizing Dose Test Report

The purpose of this test was to characterize the Avalanche Technology ASV016204’s total dose response. In the test, the device was exposed to high dose rate (HDR) irradiations using gamma radiation. Device functionality (in terms of memory cell upsets and read/write ability) as well as power supply currents during various modes of operations were recorded.

Total Ionizing Dose (TID)↗
DOE OSTI2010

Elastic Metal Alloy Refrigerants: Thermoelastic Cooling

BEETIT Project: UMD is developing an energy-efficient cooling system that eliminates the need for synthetic refrigerants that harm the environment. More than 90% of the cooling and refrigeration systems in the U.S. today use vapor compression systems which rely on liquid to vapor phase transformation of synthetic refrigerants to absorb or release heat. Thermoelastic cooling systems, however, use a solid-state material—an elastic shape memory metal alloy—as a refrigerant and a solid to solid phase transformation to absorb or release heat. UMD is developing and testing shape memory alloys and a cooling device that alternately absorbs or creates heat in much the same way as a vapor compression system, but with significantly less energy and a smaller operational footprint.

ARPA-E↗
DOE OSTI2020

Device and method for cache utilization aware data compression

A processing device is provided which includes memory and at least one processor. The memory includes main memory and cache memory in communication with the main memory via a link. The at least one processor is configured to receive a request for a cache line and read the cache line from main memory. The at least one processor is also configured to compress the cache line according to a compression algorithm and, when the compressed cache line includes at least one byte predicted not to be accessed, drop the at least one byte from the compressed cache line based on whether the compression algorithm is determined to successfully compress the cache line according to a compression parameter.

Das, Shomit N.↗