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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,063 records · Page 59
All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

Advanced Utilization of the Payload Executive Processor (PEP) Ethernet Port to Support JSL Based Payloads

Increased interest by Payload Developers in utilization of the Joint Station LAN (Local Area Network) (JSL) for command and data transactions has driven the investigation of providing bi-directional Ethernet communication with PEP (Payload Executive Processor). Ethernet-only payload developers are interested in taking advantage of the services provided by PEP. Enabling Ethernet communications within PEP requires more than just turning on the hardware. PEP contains no Operating System (OS) or Ethernet stack so it does not inherit any built in functionality for Ethernet support. Both hardware drivers and application software must be developed from scratch. In the absence of an OS (Operating System) the design must address security issues in terms of access and data transferred, i.e. blocking unauthorized users and preventing denial of service. Developing a design to process Ethernet data within the existing real-time constraints of PEP requires a few compromises: data rates, supported protocols, custom packet format and limited client connections to name a few. Integration of the light weight internet protocol (LwIP). Ethernet stack provides a customizable solution for the embedded real-time environment. As utilization of the JSL increases, the successful implementation of an Ethernet interface enhances the utilization of PEP, and provides a new path for future Ethernet-only payloads to gain access to around the clock command and data services.

Guyette, Greg↗
NASA NTRS1990

Parallel asynchronous hardware implementation of image processing algorithms

Research is being carried out on hardware for a new approach to focal plane processing. The hardware involves silicon injection mode devices. These devices provide a natural basis for parallel asynchronous focal plane image preprocessing. The simplicity and novel properties of the devices would permit an independent analog processing channel to be dedicated to every pixel. A laminar architecture built from arrays of the devices would form a two-dimensional (2-D) array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuron-like asynchronous pulse-coded form through the laminar processor. No multiplexing, digitization, or serial processing would occur in the preprocessing state. High performance is expected, based on pulse coding of input currents down to one picoampere with noise referred to input of about 10 femtoamperes. Linear pulse coding has been observed for input currents ranging up to seven orders of magnitude. Low power requirements suggest utility in space and in conjunction with very large arrays. Very low dark current and multispectral capability are possible because of hardware compatibility with the cryogenic environment of high performance detector arrays. The aforementioned hardware development effort is aimed at systems which would integrate image acquisition and image processing.

Coon, Darryl D.↗
NASA NTRS1988

The Alaska SAR processor

The Alaska SAR processor was designed to process over 200 100 km x 100 km (Seasat like) frames per day from the raw SAR data, at a ground resolution of 30 m x 30 m from ERS-1, J-ERS-1, and Radarsat. The near real time processor is a set of custom hardware modules operating in a pipelined architecture, controlled by a general purpose computer. Input to the processor is provided from a high density digital cassette recording of the raw data stream as received by the ground station. A two pass processing is performed. During the first pass clutter-lock and auto-focus measurements are made. The second pass uses the results to accomplish final image formation which is recorded on a high density digital cassette. The processing algorithm uses fast correlation techniques for range and azimuth compression. Radiometric compensation, interpolation and deskewing is also performed by the processor. The standard product of the ASP is a high resolution four-look image, with a low resolution (100 to 200 m) many look image provided simultaneously.

Carande, R. E.↗
NASA NTRS1987

Synthetic aperture radar signal processing on the MPP

Satellite-borne Synthetic Aperture Radars (SAR) sense areas of several thousand square kilometers in seconds and transmit phase history signal data several tens of megabits per second. The Shuttle Imaging Radar-B (SIR-B) has a variable swath of 20 to 50 km and acquired data over 100 kms along track in about 13 seconds. With the simplification of separability of the reference function, the processing still requires considerable resources; high speed I/O, large memory and fast computation. Processing systems with regular hardware take hours to process one Seasat image and about one hour for a SIR-B image. Bringing this processing time closer to acquisition times requires an end-to-end system solution. For the purpose of demonstration, software was implemented on the present Massively Parallel Processor (MPP) configuration for processing Seasat and SIR-B data. The software takes advantage of the high processing speed offered by the MPP, the large Staging Buffer, and the high speed I/O between the MPP array unit and the Staging Buffer. It was found that with unoptimized Parallel Pascal code, the processing time on the MPP for a 4096 x 4096 sample subset of signal data ranges between 18 and 30.2 seconds depending on options.

Ramapriyan, H. K.↗
DOE OSTI2020

Bringing heterogeneity to the CMS software framework

The advent of computing resources with co-processors, for example Graphics Processing Units (GPU) or Field-Programmable Gate Arrays (FPGA), for use cases like the CMS High-Level Trigger (HLT) or data processing at leadership-class supercomputers imposes challenges for the current data processing frameworks. These challenges include developing a model for algorithms to offload their computations on the co-processors as well as keeping the traditional CPU busy doing other work. The CMS data processing framework, CMSSW, implements multithreading using the Intel Threading Building Blocks (TBB) library, that utilizes tasks as concurrent units of work. In this paper we will discuss a generic mechanism to interact effectively with non-CPU resources that has been implemented in CMSSW. In addition, configuring such a heterogeneous system is challenging. In CMSSW an application is configured with a configuration file written in the Python language. The algorithm types are part of the configuration. The challenge therefore is to unify the CPU and co-processor settings while allowing their implementations to be separate. We will explain how we solved these challenges while minimizing the necessary changes to the CMSSW framework. We will also discuss on a concrete example how algorithms would offload work to NVIDIA GPUs using directly the CUDA API.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1991

Performance of hashed cache data migration schemes on multicomputers

After conducting an examination of several data-migration mechanisms which permit an explicit and controlled mapping of data to memory, a set of schemes for storage and retrieval of off-processor array elements is experimentally evaluated and modeled. All schemes considered have their basis in the use of hash tables for efficient access of nonlocal data. The techniques in question are those of hashed cache, partial enumeration, and full enumeration; in these, nonlocal data are stored in hash tables, so that the operative difference lies in the amount of memory used by each scheme and in the retrieval mechanism used for nonlocal data.

Hiranandani, Seema↗
DOE OSTI2014

Modelling excitonic-energy transfer in light-harvesting complexes

The theoretical and experimental study of energy transfer in photosynthesis has revealed an interesting transport regime, which lies at the borderline between classical transport dynamics and quantum-mechanical interference effects. Dissipation is caused by the coupling of electronic degrees of freedom to vibrational modes and leads to a directional energy transfer from the antenna complex to the target reaction-center. The dissipative driving is robust and does not rely on fine-tuning of specific vibrational modes. For the parameter regime encountered in the biological systems new theoretical tools are required to directly compare theoretical results with experimental spectroscopy data. The calculations require to utilize massively parallel graphics processor units (GPUs) for efficient and exact computations.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2017

GPU-based parallel algorithm for generating massive scale-free networks using the preferential attachment model

A novel parallel algorithm is presented for generating random scale-free networks using the preferential-attachment model. The algorithm, named cuPPA, is custom-designed for single instruction multiple data (SIMD) style of parallel processing supported by modern processors such as graphical processing units (GPUs). To the best of our knowledge, our algorithm is the first to exploit GPUs, and also the fastest implementation available today, to generate scale-free networks using the preferential attachment model. A detailed performance study is presented to understand the scalability and runtime characteristics of the cuPPA algorithm. In one of the best cases, when executed on an NVidia GeForce 1080 GPU, cuPPA generates a scale-free network of two billion edges in less than 3 seconds.

Alam, Maksudul↗
DOE OSTI2017

Generating Billion-Edge Scale-Free Networks in Seconds: Performance Study of a Novel GPU-based Preferential Attachment Model

A novel parallel algorithm is presented for generating random scale-free networks using the preferential-attachment model. The algorithm, named cuPPA, is custom-designed for single instruction multiple data (SIMD) style of parallel processing supported by modern processors such as graphical processing units (GPUs). To the best of our knowledge, our algorithm is the first to exploit GPUs, and also the fastest implementation available today, to generate scale free networks using the preferential attachment model. A detailed performance study is presented to understand the scalability and runtime characteristics of the cuPPA algorithm. In one of the best cases, when executed on an NVidia GeForce 1080 GPU, cuPPA generates a scale free network of a billion edges in less than 2 seconds.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Sparse Matrix-Matrix Multiplication on Multilevel Memory Architectures: Algorithms and Experiments

Architectures with multiple classes of memory media are becoming a common part of mainstream supercomputer deployments. So called multi-level memories offer differing characteristics for each memory component including variation in bandwidth, latency and capacity. This paper investigates the performance of sparse matrix multiplication kernels on two leading highperformance computing architectures — Intel's Knights Landing processor and NVIDIA's Pascal GPU. We describe a data placement method and a chunking-based algorithm for our kernels that exploits the existence of the multiple memory spaces in each hardware platform. We evaluate the performance of these methods w.r.t. standard algorithms using the auto-caching mechanisms Our results show that standard algorithms that exploit cache reuse performed as well as multi-memory-aware algorithms for architectures such as Ki\iLs where the memory subsystems have similar latencies. However, for architectures such as GPUS where memory subsystems differ significantly in both bandwidth and latency, multi-memory-aware methods are crucial for good performance. In addition, our new approaches permit the user to run problems that require larger capacities than the fastest memory of each compute node without depending on the software-managed cache mechanisms.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Final Report for CRADA SC16/01880.00

In this project, Sandia National Laboratories (SNL) and Rigetti Quantum Computing (RQC) collaborated to test and evaluate (T&E) an 8-qubit quantum information processor developed by RQC. SNL provided quantum circuits and data analysis protocols to benchmark the performance of the device. These protocols included gate-set tomography (GST) on 1- and 2-qubit subsystems, as well as more advanced protocols for characterizing crosstalk and drift. RQC provided high- and low-level access to the 8-qubit device, via direct collaboration: SNL was able to specify T&E experiments as lists of quantum circuits, delivered to RQC via email, and RQC then ran these experiments and delivered the resulting data back to SNL for analysis. The collaboration characterized the performance of all 1-qubit gates on all 8 qubits, and a sample 2-qubit gate on one pair of qubits. Extensive investigation of crosstalk produced nondefinitive results, and revealed significant drift that interfered with crosstalk detection. Drift was analyzed. As a result of this collaboration, SNL was able to test protocols for crosstalk and drift, and improve them in light of experimental data, while RQC was able to learn about the performance of their device and improve it by debugging.

Blume-Kohout, Robin↗
DOE OSTI2020

Screening IMS Seismic Detections using Dynamic Correlation Processor: Progress report for 2020

LLNL completed the FY20 workplan entailing application of the Dynamic Correlation Processor (DCP) to International Monitoring System (IMS) primary seismic data in 2019 and 2020. The effective analysis period was curtailed to January 1 through November 12, 2019 due to a data compression change that rendered later data unusable. Fixing the data compression error is a priority for our data source, and we plan to extend the period of data analysis when the fix is implemented. We found that the percentage overlap between detections generated by the International Data Centre (IDC) DFX software and detections generated by DCP varied widely by station. Overlap is 30-40% at some stations, suggesting that a large percentage of DFX detections could be screened (removed) from the detection-event association algorithm. However, detection overlap was much lower, a few percent, at many stations and the percentage overlap was low at stations known to have many mines and other local sources of seismicity. Unexpectedly low detection overlap at many stations prompted us to examine results for the ARCES station in detail. There is considerable mine activity near ARCES, but our initial FY20 analysis found only ~2% DCP/DFX detection overlap. Differences in the pre-processing (e.g. beam recipes) used by DCP and DFX appear to be the cause of low detection overlap at ARCES. DCP uses wideband filters to improve detector robustness and the IDC uses narrow-band pre-filtering to improve sensitivity. After reprocessing ARCES using the IDC beam recipe, DCP/DFX overlap increased to ~74%. This result shows that we must reprocess the IMS network using the IDC station-specific beam recipes if we are to effectively screen DFX detections and improve automatic event building performance at the IDC.

58 GEOSCIENCES↗
NASA NTRS1975

Space Tug Avionics Definition Study. Volume 5: Cost and Programmatics

The baseline avionics system features a central digital computer that integrates the functions of all the space tug subsystems by means of a redundant digital data bus. The central computer consists of dual central processor units, dual input/output processors, and a fault tolerant memory, utilizing internal redundancy and error checking. Three electronically steerable phased arrays provide downlink transmission from any tug attitude directly to ground or via TDRS. Six laser gyros and six accelerometers in a dodecahedron configuration make up the inertial measurement unit. Both a scanning laser radar and a TV system, employing strobe lamps, are required as acquisition and docking sensors. Primary dc power at a nominal 28 volts is supplied from dual lightweight, thermally integrated fuel cells which operate from propellant grade reactants out of the main tanks.

Source record↗
NASA NTRS1978

Modular on-board adaptive imaging

Feature extraction involves the transformation of a raw video image to a more compact representation of the scene in which relevant information about objects of interest is retained. The task of the low-level processor is to extract object outlines and pass the data to the high-level process in a format that facilitates pattern recognition tasks. Due to the immense computational load caused by processing a 256x256 image, even a fast minicomputer requires a few seconds to complete this low-level processing. It is, therefore, necessary to consider hardware implementation of these low-level functions to achieve real-time processing speeds. The considered project had the objective to implement a system in which the continuous feature extraction process is not affected by the dynamic changes in the scene, varying lighting conditions, or object motion relative to the cameras. Due to the high bandwidth (3.5 MHz) and serial nature of the TV data, a pipeline processing scheme was adopted as the overall architecture of this system. Modularity in the system is achieved by designing circuits that are generic within the overall system.

Eskenazi, R.↗
NASA NTRS1982

The P-POD Project

The programmable pilot oriented display (P-POD), a multiprocessor based flight information processing and display unit, is discussed. Communication protocols between the three Z-80 processors inside P-POD are reviewed. The interface between the video processor, P2, and the main processor, P1, was tested. Hardware and software were revised. Data flow between P1 and P2 is illustrated. While running diagnostic routines to exercise the P1/P2 interface at maximum speed an intermittent failure was observed. A check of possible noise sources or race conditions in the hardware did not reveal the source of this failure. Possible software timing problems were also fully investigated. To eliminate the effects of this type of failure a performance monitor routine was used to detect these occasional failures and correct them. The data transmission cycle between P1/P2 is either allowed to continue normal operation or is re-initialized and restarted when an error is detected.

Littlefield, J. A.↗
NASA NTRS1982

Combining analysis with optimization at Langley Research Center - An evolutionary process

Analytical and computational advances, at Langely Research Center (La RC), contributing to the evolution of computer programs combining analysis and optimization are presented, namely, strength sizing, concurrent strength and flutter sizing, and general optimization. Current work on a software system which executes the analysis and optimization in a sequential rather than concurrent mode is then described, as a step toward the long-term goal at La RC of developing the methodology for such systems. The software system is designated Enginering Analysis Language (EAL)/Programming Structural Synthesis System (PR)SSS), and work is being done on the incorporation of PROSSS into EAL. EAL language can perform most FORTRAN operations, including testing, branching, and looping, and its data base system can easily be accessed by any processor using FORTRAN callable utility subroutines. Some numerical results showing the accuracy of EAL/PROSSS are given.

Rogers, J. L., Jr.↗
NASA NTRS1986

Modular, Fast, Two-Dimensional Cyclic Convolver

Proposed high-throughput, real-time synthetic-aperture-radar (SAR) processor built using new, modular, two-dimensional cyclic convolver architecture based on polynomial factorization and designed for very-large-scale integrated (VLSI) circuitry. New architecture reduces cost, size, and power dissipation of SAR processor in comparison to high-speed array-processor approach. Processor also used for other image-and data-processing applications involving two-dimensional Fourier transforms.

Liu, K. Y.↗
NASA NTRS1985

Algorithms and programming tools for image processing on the MPP

Topics addressed include: data mapping and rotational algorithms for the Massively Parallel Processor (MPP); Parallel Pascal language; documentation for the Parallel Pascal Development system; and a description of the Parallel Pascal language used on the MPP.

Reeves, A. P.↗