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At least 1,045 records · Page 58
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Microelectronics↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Microelectronics↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
NASA NTRS2016

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

JFET↗
NASA NTRS2017

Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

Baranauskas, Dalius↗
NASA NTRS2006

THz multiplier circuits

Planar Schottky diode technology has been utilized to fabricate high-power broad-band monolithic multiplier circuits that can produce appreciable power well into the THz range. The chip fabrication technology that has been developed allows for robust circuit designs that can be easily packaged in conventional waveguide blocks. An overview of the capability of GaAs based Schottky diode multipliers will be presented.

Maestrini, A.↗
NASA NTRS2009

Irradiation with molecular hydrogen as an accelerated total dose hardness assurance test method for bipolar linear circuits

High dose rate irradiation with hydrogen stress is proposed as an accelerated total dose test method for bipolar linear circuits. The method is validated across process and circuit technologies with five parts that are commonly used in space: a comparator (LM193 from National Semi-conductor), a voltage regulator (HSYE-117 RH from Intersil), a voltage reference (LT1019 from Linear Technology), a JFET input op amp (OP42 from Analog Devices) and a temperature transducer (AD590 from Analog Devices). The testing technique could rapidly establish an upper bound to the low dose rate response of parts in space and help with the part selection process in the design phase of a mission. The technology dependence and the viability of this technique are qualitatively explored using a physical model describing the dose rate response and the effect of hydrogen in bipolar technologies. The model uses four core processes: 1) space charge effects, 2) free electron/hole pair recombination, hole-hydrogen defect reactions in the oxides and 4) proton depassivation of dangling bonds at the Si/SiO2 interface. Radiation hardness assurance implications are discussed.

Pease, Ron↗
NASA NTRSDate not supplied

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

DC Powered Oven↗
NASA NTRSDate not supplied

Photonic Integrated Circuit TUned for Reconnaissance and Exploration (PICTURE)

The mid-infrared (MIR) spectral range (3-5 μm) is of particular interest for remotely sensing gaseous molecules such as H2O, CO2, CH4, N2O, CO, NH3, and other compounds. The infrared spectra of planets, moons, comets, and asteroids are rich in information, including gas composition and surface mineralogy. Significant advances in technology have emerged for ground-based telescopes, including the higher spectral resolution permitted by cross-dispersed instruments and heterodyne techniques. New technologies offer the opportunity to break this barrier, by using solid- state photonics. In the past three years, under the NASA ROSES PICASSO program, we have been developing key components for a revolutionary MIR spectrometer: Photonic Integrated Circuit TUned for Reconnaissance and Exploration (PICTURE), which is based on integrated photonics technology that offers ultra-small size, weight, and power (SWaP) with non-moving parts and low cost for future planetary missions. In this paper, we will describe our science and technology development progress leading to demonstrating the concept and functionalities of the PICTURE instrument. The photonic integrated circuit spectrometer (PICS) of the PICTURE instrument uses an integrated heterodyne detection scheme to significantly reduce SWaP and improve sensitivity. Our program goals are to advance the building blocks needed for the PICS, which include arrayed waveguide gratings (AWGs), quantum cascade lasers (QCLs) as local oscillators, and quantum cascade detectors (QCDs) as heterodyne detectors. In addition, we are leveraging a NASA SBIR program to develop the toolsets needed to fabricate MIR photonics lanterns (PL). The PL is a critical component that enables PICTURE to bring a signal from the collecting telescope to the PICS, which requires single optical mode inputs. PICTURE focuses on the CO spectral band at 4.6-4.8 μm that is of key importance to cometary science. We also continue to explore future instrument concepts that exploit the broad wavelength potential of the PICS design to perform spectroscopy spanning the full MIR and longwave IR (LWIR) bands. This will have wide applicability in planetary science, for example, to probe the strongest CO2, H2O, and CH4 transitions that are difficult (CH4) or impossible (CO2, H2O) to detect using Earth-based telescopes due to atmospheric opacity. Each integrated-photonics-spectrometer chip will feature a single heterodyne room-temperature laser with a wide wavelength tuning range, or multiple local-oscillator lasers for much broader spectral coverage. The fully developed PICTURE instrument will provide a cost-effective, high-resolution spectrometer for future space applications.

Anthony W Yu↗
NASA NTRSDate not supplied

Photonic Integrated Circuit TUned for Reconnaissance and Exploration (PICTURE)

The mid-infrared (MIR) spectral range (3-5 μm) is of particular interest for remotely sensing gaseous molecules such as H2O, CO2, CH4, N2O, CO, NH3, and other compounds. The infrared spectra of planets, moons, comets, and asteroids are rich in information, including gas composition and surface mineralogy. Significant advances in technology have emerged for ground-based telescopes, including the higher spectral resolution permitted by cross-dispersed instruments and heterodyne techniques. New technologies offer the opportunity to break this barrier, by using solid-state photonics. In the past three years, under the NASA ROSES PICASSO program, we have been developing key components for a revolutionary MIR spectrometer: Photonic Integrated Circuit TUned for Reconnaissance and Exploration (PICTURE), which is based on integrated photonics technology that offers ultra-small size, weight, and power (SWaP) with non-moving parts and low cost for future planetary missions. In this paper, we will describe our science and technology development progress leading to demonstrating the concept and functionalities of the PICTURE instrument. The photonic integrated circuit spectrometer (PICS) of the PICTURE instrument uses an integrated heterodyne detection scheme to significantly reduce SWaP and improve sensitivity. Our program goals are to advance the building blocks needed for the PICS, which include arrayed waveguide gratings (AWGs), quantum cascade lasers (QCLs) as local oscillators, and quantum cascade detectors (QCDs) as heterodyne detectors. In addition, we are leveraging a NASA SBIR program to develop the toolsets needed to fabricate MIR photonics lanterns (PL). The PL is a critical component that enables PICTURE to bring a signal from the collecting telescope to the PICS, which requires single optical mode inputs. PICTURE focuses on the CO spectral band at 4.6-4.8 μm that is of key importance to cometary science. We also continue to explore future instrument concepts that exploit the broad wavelength potential of the PICS design to perform spectroscopy spanning the full MIR and longwave IR (LWIR) bands. This will have wide applicability in planetary science, for example, to probe the strongest CO2, H2O, and CH4 transitions that are difficult (CH4) or impossible (CO2, H2O) to detect using Earth-based telescopes due to atmospheric opacity. Each integrated-photonics-spectrometer chip will feature a single heterodyne room-temperature laser with a wide wavelength tuning range, or multiple local-oscillator lasers for much broader spectral coverage. The fully developed PICTURE instrument will provide a cost-effective, high-resolution spectrometer for future space applications.

Anthony W Yu↗
NASA NTRS2023

NASA Engineering and Safety Center Technical Bulletin No. 23-01: Including Key Design Features in Safety-Critical Pyrotechnic Firing Circuits

Pyrotechnic systems often fall into a unique category in that inadvertent activation of these systems resulting from a fault and/or lack of safe margins can lead directly to loss of crew. For example, untimely activation of pyrotechnics used for a flight termination system could override an abort capability. Over the years, NASA and the military have learned lessons about safe pyrotechnic circuit design and test, many of which are codified. However, with NASA’s recent efforts to move toward a development model than leans more heavily on Commercial Partners these requirements have not always been directly levied on projects and in some cases been misinterpreted. This bulletin describes key safety features of pyrotechnic firing circuit design and provides rationale for inclusion of each feature.

Pyrotechnic Firing Curcuits↗
NASA NTRSDate not supplied

Photonic Integrated Circuit TUned for Reconnaissance and Exploration (PICTURE)

The mid-infrared (MIR) spectral range (3-5 μm) is of particular interest for remotely sensing gaseous molecules such as H2O, CO2, CH4, N2O, CO, NH3, and other compounds. The infrared spectra of planets, moons, comets, and asteroids are rich in information, including gas composition and surface mineralogy. Significant advances in technology have emerged for ground-based telescopes, including the higher spectral resolution permitted by cross-dispersed instruments and heterodyne techniques. New technologies offer the opportunity to break this barrier, by using solid-state photonics. In the past three years, under the NASA ROSES PICASSO program, we have been developing key components for a revolutionary MIR spectrometer: Photonic Integrated Circuit TUned for Reconnaissance and Exploration (PICTURE), which is based on integrated photonics technology that offers ultra-small size, weight, and power (SWaP) with non-moving parts and low cost for future planetary missions. In this paper, we will describe our science and technology development progress leading to demonstrating the concept and functionalities of the PICTURE instrument. The photonic integrated circuit spectrometer (PICS) of the PICTURE instrument uses an integrated heterodyne detection scheme to significantly reduce SWaP and improve sensitivity. Our program goals are to advance the building blocks needed for the PICS, which include arrayed waveguide gratings (AWGs), quantum cascade lasers (QCLs) as local oscillators, and quantum cascade detectors (QCDs) as heterodyne detectors. In addition, we are leveraging a NASA SBIR program to develop the toolsets needed to fabricate MIR photonics lanterns (PL). The PL is a critical component that enables PICTURE to bring a signal from the collecting telescope to the PICS, which requires single optical mode inputs. PICTURE focuses on the CO spectral band at 4.6-4.8 μm that is of key importance to cometary science. We also continue to explore future instrument concepts that exploit the broad wavelength potential of the PICS design to perform spectroscopy spanning the full MIR and longwave IR (LWIR) bands. This will have wide applicability in planetary science, for example, to probe the strongest CO2, H2O, and CH4 transitions that are difficult (CH4) or impossible (CO2, H2O) to detect using Earth-based telescopes due to atmospheric opacity. Each integrated-photonics-spectrometer chip will feature a single heterodyne room-temperature laser with a wide wavelength tuning range, or multiple local-oscillator lasers for much broader spectral coverage. The fully developed PICTURE instrument will provide a cost-effective, high-resolution spectrometer for future space applications.

Anthony W. Yu↗
NASA NTRS2024

Two mechanisms for the spontaneous emergence, execution, and reprogramming of chemical logic circuits

A key question in origin-of-life research is how primitive life or life-like systems obtained reusable and reprogrammable machinery of processing information to respond to various environmental and internal stimuli. One strategy to approach this question is to view living systems as universal chemical computers. This approach focuses upon uncovering how reusable and reprogrammable chemical NOT, AND, and OR logic gates could appear under prebiotically possible scenarios where simple chemicals and second- or lower-order reactions are more frequent than macromolecules and higher-order reactions. In this article, we theoretically model two generic mechanisms of forming Boolean gates based on geochemically plausible reaction systems that could have preceded complex biopolymers. The mechanisms exploit simple bistable autocatalytic systems to encode binary variables and use heterogeneous dilution rates to differentially activate or deactivate autocatalysis in different reactors. We found that NOT, AND, and OR gates, as well as more complex logic circuits, can spontaneously arise from connected, well-mixed flow reactors based on (i) catalysis by a heterodimer between mutually inhibitory autocatalysts or (ii) selectively permeable tunnels connecting reactors. Our results suggest that simple machinery can support the prebiotic emergence of complex chemical logic circuits and provide new guides for experimentally actualizing chemical computation.

Zhen Peng↗
DOE OSTI2020

Offset-aligned three-dimensional integrated circuit

A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

42 ENGINEERING↗
DOE OSTI2020

Electrical circuit control in power systems

Electrical circuit control techniques in power systems are disclosed herein. In one embodiment, a supervisory computer in the power system can be configured to fit phasor measurement data from phasor measurement units into a Gaussian distribution with a corresponding Gaussian confidence level. When the Gaussian confidence level of the fitted Gaussian distribution is above a Gaussian confidence threshold, the supervisory computer can be configured to perform an ambient analysis on the received phasor measurement data to determine an operating characteristic of the power system. The supervisory computer can then automatically applying at least one electrical circuit control action to the power system in response to the determined operating characteristic.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Density Matrix Quantum Circuit Simulation via the BSP Machine on Modern GPU Clusters

As quantum computers evolve, simulations of quantum programs on classical computers will be essential in validating quantum algorithms, understanding the effect of system noise, and design applications for future quantum computers. In this paper, we propose a novel multi-GPU programming model called MG-BSP that constructs a virtual BSP machine on top of modern multi-GPU platforms, and tweak the programming model to build a multi-GPU density matrix quantum simulator. We propose and evaluated a new formulation minimizing communication and prove that the transformation conserves original semantics when noise is introduced. We build the tool-chain to support quantum assembly open standard, synthesize testing quantum circuit, and enable ultra-deep quantum simulation. We evaluated our design on four state-of-the-art multi-GPU platforms including the latest DGX-1 and DGX-2 systems. We demonstrate simulation of 1 million gates in 94 minutes, far deeper circuits than has been demonstrated in prior work. A roofline-model analysis show that we have reached near-optimal performance under memory bound.

Li, Ang↗