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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,045 records · Page 58
All sourcesNASA NTRSDOE OSTI
NASA NTRS1997

III-V aresenide-nitride semiconductor materials and devices

III-V arsenide-nitride semiconductor crystals, methods for producing such crystals and devices employing such crystals. Group III elements are combined with group V elements, including at least nitrogen and arsenic, in concentrations chosen to lattice match commercially available crystalline substrates. Epitaxial growth of these III-V crystals results in direct bandgap materials, which can be used in applications such as light emitting diodes and lasers. Varying the concentrations of the elements in the III-V crystals varies the bandgaps, such that materials emitting light spanning the visible spectra, as well as mid-IR and near-UV emitters, can be created. Conversely, such material can be used to create devices that acquire light and convert the light to electricity, for applications such as full color photodetectors and solar energy collectors. The growth of the III-V crystals can be accomplished by growing thin layers of elements or compounds in sequences that result in the overall lattice match and bandgap desired.

Major, Jo S.↗
NASA NTRS2004

Catalyst patterning for nanowire devices

Nanowire devices may be provided that are based on carbon nanotubes or single-crystal semiconductor nanowires. The nanowire devices may be formed on a substrate. Catalyst sites may be formed on the substrate. The catalyst sites may be formed using lithography, thin metal layers that form individual catalyst sites when heated, collapsible porous catalyst-filled microscopic spheres, microscopic spheres that serve as masks for catalyst deposition, electrochemical deposition techniques, and catalyst inks. Nanowires may be grown from the catalyst sites.

Li, Jun↗
NASA NTRS1995

Method for fabricating semiconductor devices

A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term in situ herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed. An alternative embodiment of the present invention comprising an additional step, namely the termination of the gallium arsenide by a two monolayer thickness of epitaxial aluminum arsenide as a diffusion barrier, enables the recovery of Schottky barrier behavior, namely a rectified I-V characteristic. The present invention provides a significant breakthrough in the fabrication of III-V semiconductor devices wherein excellent Ohmic contact and Schottky barrier interfaces to such devices can be achieved simply and inexpensively and without requiring the high temperature processing of the prior art and also without requiring the use of exotic high temperature refractory materials as substitutes for those preferred contact metals such as gold, aluminum and the like.

Kaiser, William J.↗
NASA NTRS1987

Semiconductor structure and devices

Semiconductor devices such as lasers which include a substrate with a channel therein with a clad layer overlying the substrate and filling the channel exhibit irregularities such as terraces in the surface of the clad layer which are detrimental to device performance. These irregularities are substantially eliminated by forming the channel in a surface of a buffer layer greater than about 4 micrometers thick on the substrate and forming the clad layer over the buffer layer and the channel. CW lasers incorporating the principles of the invention exhibit the highest output power in a single spatial mode and maximum output power which have been observed to date.

Dinkel, Nancy A.↗
NASA NTRS2006

Sensing device and method for measuring emission time delay during irradiation of targeted samples utilizing variable phase tracking

An apparatus for measuring emission time delay during irradiation of targeted samples by utilizing digital signal processing to determine the emission phase shift caused by the sample is disclosed. The apparatus includes a source of electromagnetic radiation adapted to irradiate a target sample. A mechanism generates first and second digital input signals of known frequencies with a known phase relationship, and a device then converts the first and second digital input signals to analog sinusoidal signals. An element is provided to direct the first input signal to the electromagnetic radiation source to modulate the source by the frequency thereof to irradiate the target sample and generate a target sample emission. A device detects the target sample emission and produces a corresponding first output signal having a phase shift relative to the phase of the first input signal, the phase shift being caused by the irradiation time delay in the sample. A member produces a known phase shift in the second input signal to create a second output signal. A mechanism is then provided for converting each of the first and second analog output signals to digital signals. A mixer receives the first and second digital output signals and compares the signal phase relationship therebetween to produce a signal indicative of the change in phase relationship between the first and second output signals caused by the target sample emission. Finally, a feedback arrangement alters the phase of the second input signal based on the mixer signal to ultimately place the first and second output signals in quadrature. Mechanisms for enhancing this phase comparison and adjustment technique are also disclosed.

Danielson, J. D. Sheldon↗
NASA NTRS2006

Design of a Multi-Level/Analog Ferroelectric Memory Device

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗
NASA NTRS1978

Photovoltaic device having an extended PN junction

A photovoltaic device having essentially only a body of semiconductor material having a first region of one conductivity type in contact with a second region of the opposite conductivity type, forming a portion of the device PN junction therebetween. A plurality of pocket regions of the same conductivity type as the first region extend into the second region thereby further defining a portion of the PN junction in the second region.

D'Aiello, Robert Vincent↗
NASA NTRS2008

Devices and methods of operation thereof for providing stable flow for centrifugal compressors

Centrifugal compressor flow stabilizing devices and methods of operation thereof are disclosed that act upon the flow field discharging from the impeller of a centrifugal compressor and modify the flow field ahead of the diffuser vanes such that flow conditions contributing to rotating stall and surge are reduced or even eliminated. In some embodiments, shaped rods and methods of operation thereof are disclosed, whereas in other embodiments reverse-tangent air injection devices and methods are disclosed.

Skoch, Gary J.↗
NASA NTRS2008

Icy Soil Acquisition Device for the 2007 Phoenix Mars Lander

The Icy Soil Acquisition Device is a first of its kind mechanism that is designed to acquire ice-bearing soil from the surface of the Martian polar region and transfer the samples to analytical instruments, playing a critical role in the potential discovery of existing water on Mars. The device incorporates a number of novel features that further the state of the art in spacecraft design for harsh environments, sample acquisition and handling, and high-speed low torque mechanism design.

Chu, Philip↗
NASA NTRS2008

Device-Orientation Effects on Multiple-Bit Upset in 65-nm SRAMs

Heavy ion irradiations have been performed: a) SEU varies little with angle of ion incidence b) MBU depend on the device orientation. The MBU response depends on the well orientation of the device. MRED simulation of an omni-directional GEO environment shows the MBU response to be a combination of response from different orientations. Testing and simulation must account for multiple orientations.

Tipton, Alan D.↗
NASA NTRS2008

Liquid Acquisition Device Testing with Sub-Cooled Liquid Oxygen

When transferring propellant in space, it is most efficient to transfer single phase liquid from a propellant tank to an engine. In earth s gravity field or under acceleration, propellant transfer is fairly simple. However, in low gravity, withdrawing single-phase fluid becomes a challenge. A variety of propellant management devices (PMD) are used to ensure single-phase flow. One type of PMD, a liquid acquisition device (LAD) takes advantage of capillary flow and surface tension to acquire liquid. Previous experimental test programs conducted at NASA have collected LAD data for a number of cryogenic fluids, including: liquid nitrogen (LN2), liquid oxygen (LOX), liquid hydrogen (LH2), and liquid methane (LCH4). The present work reports on additional testing with sub-cooled LOX as part of NASA s continuing cryogenic LAD development program. Test results extend the range of LOX fluid conditions examined, and provide insight into factors affecting predicting LAD bubble point pressures.

Jurns, John M.↗
NASA NTRS2008

Scaling of Performance in Liquid Propellant Rocket Engine Combustion Devices

This paper discusses scaling of combustion and combustion performance in liquid propellant rocket engine combustion devices. In development of new combustors, comparisons are often made between predicted performance in a new combustor and measured performance in another combustor with different geometric and thermodynamic characteristics. Without careful interpretation of some key features, the comparison can be misinterpreted and erroneous information used in the design of the new device. This paper provides a review of this performance comparison, including a brief review of the initial liquid rocket scaling research conducted during the 1950s and 1960s, a review of the typical performance losses encountered and how they scale, a description of the typical scaling procedures used in development programs today, and finally a review of several historical development programs to see what insight they can bring to the questions at hand.

Hulka, James R.↗
NASA NTRS2008

Advanced resistive exercise device

The present invention relates to an exercise device, which includes a vacuum cylinder and a flywheel. The flywheel provides an inertial component to the load, which is particularly well suited for use in space as it simulates exercising under normal gravity conditions. Also, the present invention relates to an exercise device, which has a vacuum cylinder and a load adjusting armbase assembly.

Raboin, Jasen L.↗
NASA NTRS2007

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗