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At least 1,027 records · Page 57
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Management of the Post-Shuttle Extravehicular Mobility Unit (EMU) Water Circuits

The EMU incorporates two separate water circuits for the rejection of metabolic heat from the astronaut and the cooling of electrical components. The first (the Transport Water Loop) circulates in a semi-closed-loop manner and absorbs heat into a Liquid Coolant and Ventilation Garment (LCVG) worn by the astronaut. The second (the Feed-water Loop) provides water to a cooling device (Sublimator) with a porous plate, and that water subsequently sublimates to space vacuum. The cooling effect from the sublimation of this water translates to a cooling of the LCVG water that circulates through the Sublimator. Efforts are underway to streamline the use of a water processing kit (ALCLR) that is being used to periodically clean and disinfect the Transport Loop Water. Those efforts include a fine tuning of the duty cycle based on a review of prior performance data as well as an assessment of a fixed installation of this kit into the EMU backpack, within on-orbit EMU interface hardware or as a stand-alone unit. Furthermore, testing is being conducted to ensure compatibility between the International Space Station (ISS) Water Processor Assembly (WPA) effluent and the EMU Sublimator as a prelude to using the WPA effluent as influent to the EMU Feed Water loop. This work is undertaken to reduce the crewtime and logistics burdens for the EMU, while ensuring the long-term health of the EMU water circuits for a 6-year service life.

Steele, John W.↗
NASA NTRS2012

Simple Cell Balance Circuit

A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.

Johnson, Steven D.↗
NASA NTRS2012

Sampling and Control Circuit Board for an Inertial Measurement Unit

Spacesuit navigation is one component of NASA s efforts to return humans to the Moon. Studies performed at the NASA Glenn Research Center (GRC) considered various navigation technologies and filtering approaches to enable navigation on the lunar surface. As part of this effort, microelectromechanical systems (MEMS) inertial measurement units (IMUs) were studied to determine if they could supplement a radiometric infrastructure. MEMS IMUs were included in the Lunar Extra-Vehicular Activity Crewmember Location Determination System (LECLDS) testbed during NASA s annual Desert Research and Technology Studies (D-RATS) event in 2009 and 2010. The testbed included one IMU in 2009 and three IMUs in 2010, along with a custom circuit board interfacing between the navigation processor and each IMU. The board was revised for the 2010 test, and this paper documents the design details of this latest revision of the interface circuit board and firmware.

Chelmins, David↗
NASA NTRS2012

670-GHz Schottky Diode-Based Subharmonic Mixer with CPW Circuits and 70-GHz IF

GaAs-based, sub-harmonically pumped Schottky diode mixers offer a number of advantages for array implementation in a heterodyne receiver system. Since the radio frequency (RF) and local oscillator (LO) signals are far apart, system design becomes much simpler. A proprietary planar GaAs Schottky diode process was developed that results in very low parasitic anodes that have cutoff frequencies in the tens of terahertz. This technology enables robust implementation of monolithic mixer and frequency multiplier circuits well into the terahertz frequency range. Using optical and e-beam lithography, and conventional epitaxial layer design with innovative usage of GaAs membranes and metal beam leads, high-performance terahertz circuits can be designed with high fidelity. All of these mixers use metal waveguide structures for housing. Metal machined structures for RF and LO coupling hamper these mixers to be integrated in multi-pixel heterodyne array receivers for spectroscopic and imaging applications. Moreover, the recent developments of terahertz transistors on InP substrate provide an opportunity, for the first time, to have integrated amplifiers followed by Schottky diode mixers in a heterodyne receiver at these frequencies. Since the amplifiers are developed on a planar architecture to facilitate multi-pixel array implementation, it is quite important to find alternative architecture to waveguide-based mixers.

Chattopadhyay, Goutam↗
NASA NTRS2012

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Vasile, Stefan↗
NASA NTRS2009

Tin Whisker Electrical Short Circuit Characteristics

Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that has an unknown probability associated with it. Note however that due to contact resistance electrical shorts may not occur at lower voltage levels. In our first article we developed an empirical probability model for tin whisker shorting. In this paper, we develop a more comprehensive empirical model using a refined experiment with a larger sample size, in which we studied the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From the resulting data we estimated the probability distribution of an electrical short, as a function of voltage. In addition, the unexpected polycrystalline structure seen in the focused ion beam (FIB) cross section in the first experiment was confirmed in this experiment using transmission electron microscopy (TEM). The FIB was also used to cross section two card guides to facilitate the measurement of the grain size of each card guide's tin plating to determine its finish.

Courey, Karim J.↗
NASA NTRS2008

An Empirical Model for Estimating the Probability of Electrical Short Circuits from Tin Whiskers-Part I

Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that has a currently unknown probability associated with it. Due to contact resistance, electrical shorts may not occur at lower voltage levels. In this experiment, we study the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From this data, we can estimate the probability of an electrical short, as a function of voltage, given that a free tin whisker has bridged two adjacent exposed electrical conductors. In addition, three tin whiskers grown from the same Space Shuttle Orbiter card guide used in the aforementioned experiment were cross sectioned and studied using a focused ion beam (FIB).

Courey, Karim↗
NASA NTRS2008

An Investigation of the Electrical Short Circuit Characteristics of Tin Whiskers

Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that has a currently unknown probability associated with it. Due to contact resistance electrical shorts may not occur at lower voltage levels. In this experiment, we study the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From this data we can estimate the probability of an electrical short, as a function of voltage, given that a free tin whisker has bridged two adjacent exposed electrical conductors. Also, three tin whiskers grown from the same Space Shuttle Orbiter card guide used in the aforementioned experiment were cross-sectioned and studied using a focused ion beam (FIB). The rare polycrystalline structure seen in the FIB cross section was confirmed using transmission electron microscopy (TEM). The FIB was also used to cross section two card guides to facilitate the measurement of the grain size to determine that the tin plating on the card guides had a bright finish.

Courey, Karim J.↗
NASA NTRS2007

Tin Whisker Electrical Short Circuit Characteristics Part 2

Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that has a currently unknown probability associated with it. Due to contact resistance electrical shorts may not occur at lower voltage levels. In this experiment, we study the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From this data we can estimate the probability of an electrical short, as a function of voltage, given that a free tin whisker has bridged two adjacent exposed electrical conductors. In addition, three tin whiskers grown from the same Space Shuttle Orbiter card guide used in the aforementioned experiment were cross-sectioned and studied using a focused ion beam (FIB).

Courey, Karim J.↗
NASA NTRS2013

Quasi-Linear Circuit

This work involved developing spacequalifiable switch mode DC/DC power supplies that improve performance with fewer components, and result in elimination of digital components and reduction in magnetics. This design is for missions where systems may be operating under extreme conditions, especially at elevated temperature levels from 200 to 300 degC. Prior art for radiation-tolerant DC/DC converters has been accomplished utilizing classical magnetic-based switch mode converter topologies; however, this requires specific shielding and component de-rating to meet the high-reliability specifications. It requires complex measurement and feedback components, and will not enable automatic re-optimization for larger changes in voltage supply or electrical loading condition. The innovation is a switch mode DC/DC power supply that eliminates the need for processors and most magnetics. It can provide a well-regulated voltage supply with a gain of 1:100 step-up to 8:1 step down, tolerating an up to 30% fluctuation of the voltage supply parameters. The circuit incorporates a ceramic core transformer in a manner that enables it to provide a well-regulated voltage output without use of any processor components or magnetic transformers. The circuit adjusts its internal parameters to re-optimize its performance for changes in supply voltage, environmental conditions, or electrical loading at the output

Bradley, William↗
NASA NTRS2014

Open Circuit Resonant (SansEC) Sensor Technology for Lightning Mitigation and Damage Detection and Diagnosis for Composite Aircraft Applications

Traditional methods to protect composite aircraft from lightning strike damage rely on a conductive layer embedded on or within the surface of the aircraft composite skin. This method is effective at preventing major direct effect damage and minimizes indirect effects to aircraft systems from lightning strike attachment, but provides no additional benefit for the added parasitic weight from the conductive layer. When a known lightning strike occurs, the points of attachment and detachment on the aircraft surface are visually inspected and checked for damage by maintenance personnel to ensure continued safe flight operations. A new multi-functional lightning strike protection (LSP) method has been developed to provide aircraft lightning strike protection, damage detection and diagnosis for composite aircraft surfaces. The method incorporates a SansEC sensor array on the aircraft exterior surfaces forming a "Smart skin" surface for aircraft lightning zones certified to withstand strikes up to 100 kiloamperes peak current. SansEC sensors are open-circuit devices comprised of conductive trace spiral patterns sans (without) electrical connections. The SansEC sensor is an electromagnetic resonator having specific resonant parameters (frequency, amplitude, bandwidth & phase) which when electromagnetically coupled with a composite substrate will indicate the electrical impedance of the composite through a change in its resonant response. Any measureable shift in the resonant characteristics can be an indication of damage to the composite caused by a lightning strike or from other means. The SansEC sensor method is intended to diagnose damage for both in-situ health monitoring or ground inspections. In this paper, the theoretical mathematical framework is established for the use of open circuit sensors to perform damage detection and diagnosis on carbon fiber composites. Both computational and experimental analyses were conducted to validate this new method and system for aircraft composite damage detection and diagnosis. Experimental test results on seeded fault damage coupons and computational modeling simulation results are presented. This paper also presents the shielding effectiveness along with the lightning direct effect test results from several different SansEC LSP and baseline protected and unprotected carbon fiber reinforced polymer (CFRP) test panels struck at 40 and 100 kiloamperes following a universal common practice test procedure to enable damage comparisons between SansEC LSP configurations and common practice copper mesh LSP approaches. The SansEC test panels were mounted in a LSP test bed during the lightning test. Electrical, mechanical and thermal parameters were measured during lightning attachment and are presented with post test nondestructive inspection comparisons. The paper provides correlational results between the SansEC sensors computed electric field distribution and the location of the lightning attachment on the sensor trace and visual observations showing the SansEC sensor's affinity for dispersing the lightning attachment.

Szatkowski, George N.↗
NASA NTRS2014

Circuit for Communication over DC Power Line Using High Temperature Electronics

A high temperature communications circuit includes a power conductor for concurrently conducting electrical energy for powering circuit components and transmitting a modulated data signal, and a demodulator for demodulating the data signal and generating a serial bit stream based on the data signal. The demodulator includes an absolute value amplifier for conditionally inverting or conditionally passing a signal applied to the absolute value amplifier. The absolute value amplifier utilizes no diodes to control the conditional inversion or passing of the signal applied to the absolute value amplifier.

Krasowski, Michael J.↗
NASA NTRS2013

Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

ionizing radiation↗
NASA NTRS2008

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

Neudeck, Philip G.↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗
NASA NTRS2015

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗
NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

JFET↗
NASA NTRS1973

Variable Time Base Integrator Circuit for Buffet Signal Measurements

A measurement circuit to obtain buffet data from wind tunnel models wherein a signal proportional to the average RMS value of buffet data is produced for subsequent recording. Feedback means are employed to suppress the D.C. portion of signals developed by the strain gages during dynamic testing. Automatic recording of gain settings of amplifiers employed in the circuit is also provided.

Batts, Colossie N.↗