SEARCH · Engineering Papers

Results for “Memory device”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 1,027 records · Page 57

All sources NASA NTRS DOE OSTI

DOE OSTI2021

Xyce Parallel Electronic Simulator Users' Guide (V. 7.3)

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers; A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models; Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only); Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase—a message passing parallel implementation—which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

42 ENGINEERING↗

DOE OSTI2021

Xyce Parallel Electronic Simulator Users' Guide Version 7.4

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

42 ENGINEERING↗

DOE OSTI2021

TEAM Project Review, Year 2

This report summarizes our research activities within the TEAM project between December 2020 and December 2021, funded by the ASCR Advanced Research in Quantum Computing program. During the reporting period the LLNL-MSU team has made progress on several fronts. An overarching goal of the team is to provide a comprehensive suite of software tools that can be used for the Characterize-Optimize-Compute loop needed to implement and execute algorithms on quantum devices. We are concurrently developing lightweight solvers that can be used on desktop computers to find optimal control pulses and to characterize small quantum systems (consisting of a few transmons and cavities). However, desktop computers are insufficient for simulating and characterizing larger quantum systems. We have therefore also developed parallel, distributed memory, simulators and optimization solvers, both for open and closed quantum systems. These parallel solvers have, for example, been used to study quantum optimal control for pure-state preparation, utilizing 1000’s of cores on a modern high-performance computing (HPC) platform.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2024

Xyce™ Parallel Electronic Simulator Users' Guide (V.7.9)

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

42 ENGINEERING↗

DOE OSTI2025

Xyce™ Parallel Electronic Simulator Users’ Guide, Version 7.10

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1979

LED instrument approach instruction display

A display employing light emitting diodes (LED's) was developed to demonstrate the feasibility of such displays for presenting landing and navigation information to reduce the workload of general aviation pilots during IFR flight. The display consists of a paper tape reader, digital memory, control electronics, digital latches, and LED alphanumeric displays. A presentable digital countdown clock-timer is included as part of the system to provide a convenient means of monitoring time intervals for precise flight navigation. The system is a limited capability prototype assembled to test pilot reaction to such a device under simulated IFR operation. Pilot opinion indicates that the display is helpful in reducing the IFR pilots workload when used with a runway approach plate. However, the development of a compact, low power second generation display was recommended which could present several instructions simultaneously and provide information update capability. A microprocessor-based display could fulfill these requirements.

Meredith, B. D.↗

NASA NTRS1987

Flexible structure control laboratory development and technology demonstration

An experimental structure is described which was constructed to demonstrate and validate recent emerging technologies in the active control and identification of large flexible space structures. The configuration consists of a large, 20 foot diameter antenna-like flexible structure in the horizontal plane with a gimballed central hub, a flexible feed-boom assembly hanging from the hub, and 12 flexible ribs radiating outward. Fourteen electrodynamic force actuators mounted to the hub and to the individual ribs provide the means to excite the structure and exert control forces. Thirty permanently mounted sensors, including optical encoders and analog induction devices provide measurements of structural response at widely distributed points. An experimental remote optical sensor provides sixteen additional sensing channels. A computer samples the sensors, computes the control updates and sends commands to the actuators in real time, while simultaneously displaying selected outputs on a graphics terminal and saving them in memory. Several control experiments were conducted thus far and are documented. These include implementation of distributed parameter system control, model reference adaptive control, and static shape control. These experiments have demonstrated the successful implementation of state-of-the-art control approaches using actual hardware.

Vivian, H. C.↗

NASA NTRS1999

Camera-on-a-Chip

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

Source record↗

DOE OSTI2020

Xyce Parallel Electronic Simulator Users' Guide (V.7.1)

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: 1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. 2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. 3) Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only). 4) Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase a message passing parallel implementation which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

42 ENGINEERING↗

DOE OSTI2022

Xyce™ Parallel Electronic Simulator Users' Guide, Version 7.5.

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: (1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. (2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. (3) Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only). (4) Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Xyce™ Parallel Electronic Simulator Users' Guide (V.7.6)

This manual describes the use of the Xyce™ Parallel Electronic Simulator. Xyce™ has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: (1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. (2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. (3) Device models that are specifically tailored to meet Sandia's needs, including some radiation-aware devices (for Sandia users only). (4) Object-oriented code design and implementation using modern coding practices. Xyce™ is a parallel code in the most general sense of the phrase—a message passing parallel implementation—which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel eficiency is achieved as the number of processors grows.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

Xyce™ Parallel Electronic Simulator Users’ Guide, Version 7.8

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: (1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. (2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. (3) Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). (4) Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

42 ENGINEERING↗

DOE OSTI2025

Quantum materials for nanosensing and fault-tolerant quantum computing

New concepts of symmetry related to topological order emerged from the discovery of the fractional quantum Hall effect and high-temperature superconductivity in strongly correlated electron systems. This led to the study of quantum materials-- materials exhibiting emergent quantum phenomena with no classical analogues. While these materials have engendered exciting basic materials science and physics, realizing novel devices is a key challenge in the field. The goal of this proposal is to harness the unique properties of topological materials for quantum computing and quantum sensing applications. In this project, we investigated a variety of topological superconducting platforms and identified three technologies that can benefit from their quantum properties: quantum memory, single-photon detection, and non reciprocal electronics. The platforms developed in this work will be broadly useful to National Security and Basic Science.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

NASA NTRS2000

DRAGON Grid: A Three-Dimensional Hybrid Grid Generation Code Developed

Because grid generation can consume 70 percent of the total analysis time for a typical three-dimensional viscous flow simulation for a practical engineering device, payoffs from research and development could reduce costs and increase throughputs considerably. In this study, researchers at the NASA Glenn Research Center at Lewis Field developed a new hybrid grid approach with the advantages of flexibility, high-quality grids suitable for an accurate resolution of viscous regions, and a low memory requirement. These advantages will, in turn, reduce analysis time and increase accuracy. They result from an innovative combination of structured and unstructured grids to represent the geometry and the computation domain. The present approach makes use of the respective strengths of both the structured and unstructured grid methods, while minimizing their weaknesses. First, the Chimera grid generates high-quality, mostly orthogonal meshes around individual components. This process is flexible and can be done easily. Normally, these individual grids are required overlap each other so that the solution on one grid can communicate with another. However, when this communication is carried out via a nonconservative interpolation procedure, a spurious solution can result. Current research is aimed at entirely eliminating this undesired interpolation by directly replacing arbitrary grid overlapping with a nonstructured grid called a DRAGON grid, which uses the same set of conservation laws over the entire region, thus ensuring conservation everywhere. The DRAGON grid is shown for a typical film-cooled turbine vane with 33 holes and 3 plenum compartments. There are structured grids around each geometrical entity and unstructured grids connecting them. In fiscal year 1999, Glenn researchers developed and tested the three-dimensional DRAGON grid-generation tools. A flow solver suitable for the DRAGON grid has been developed, and a series of validation tests are underway.

Liou, Meng-Sing↗

NASA NTRS1976

Intensified charge coupled devices for ultra low light level imaging

Development of a sensor incorporating a CCD and photocathode for operation in the electron bombarded mode in both a magnetic and an electrostatic focussed, gated configuration is described. Initial format size is 100 x 160 pixels with eventual growth to 400 x 400 pixels. The sensor is part of a digital camera system which includes the low level video conditioning electronics, a camera controller, a high speed buffer memory, and digital recording and display electronics. The memory uses CMOS/SOS and has a capacity of 1.6 Mbits with operating rates of 48 Mbits/sec. Individual frames are co-added to provide wide dynamic range and photometric precision better than 1%. A 4-bit video quantization is used to increase the photon counting detection rate before coincidence losses become serious.

Sobieski, S.↗

NASA NTRS2015

On the Recovery Stress of a Ni50.3Ti29.7Hf20 High Temperature Shape Memory Alloy

Recovery stress in shape memory alloys (SMAs), also known as blocking stress, is an important property generally obtained during heating under a dimensional constraint as the material undergoes the martensitic phase transformation. This property has been instinctively utilized in most SMA shape-setting procedures, and has been used in numerous applications such as fastening and joining, rock splitting, safety release mechanisms, reinforced composites, medical devices, and many other applications. The stress generation is also relevant to actuator applications where jamming loads (e.g., in case the actuator gets stuck and is impeded from moving) need to be determined for proper hardware sizing. Recovery stresses in many SMA systems have been shown to reach stresses in the order of 800 MPa, achieved via thermo-mechanical training such as pre-straining, heat treatments or other factors. With the advent of high strength, high temperature SMAs, recovery stress data has been rarely probed, and there is no information pertinent to the magnitudes of these stresses. Thus, the purpose of this work is to investigate the recovery stress capability of a precipitation strengthened, Ni50.3Ti29.7Hf20 (at.) high temperature SMA in uniaxial tension and compression. This material has been shown to exhibit outstanding strength and stability during constant-stress, thermal cycling, but no data exists on constant-strain thermal cycling. Several training routines were implemented as part of this work including isothermal pre-straining, isobaric thermal cycling, and isothermal cyclic training routines. Regardless of the training method used, the recovery stress was characterized using constant-strain (strain-controlled condition) thermal cycling between the upper and lower cycle temperatures. Preliminary results indicate recovery stresses in excess of 1.5 GPa were obtained after a specific training routine. This stress magnitude is significantly higher than conventional NiTi stress generation capability.

Recovery Stress↗

NASA NTRS1996

Evolving Requirements for Magnetic Tape Data Storage Systems

Magnetic tape data storage systems have evolved in an environment where the major applications have been back-up/restore, disaster recovery, and long term archive. Coincident with the rapidly improving price-performance of disk storage systems, the prime requirements for tape storage systems have remained: (1) low cost per MB, (2) a data rate balanced to the remaining system components. Little emphasis was given to configuring the technology components to optimize retrieval of the stored data. Emerging new applications such as network attached high speed memory (HSM), and digital libraries, place additional emphasis and requirements on the retrieval of the stored data. It is therefore desirable to consider the system to be defined both by STorage And Retrieval System (STARS) requirements. It is possible to provide comparative performance analysis of different STARS by incorporating parameters related to (1) device characteristics, and (2) application characteristics in combination with queuing theory analysis. Results of these analyses are presented here in the form of response time as a function of system configuration for two different types of devices and for a variety of applications.

Gniewek, John J.↗

NASA NTRS1999

Hierarchical Approach to 'Atomistic' 3-D MOSFET Simulation

We present a hierarchical approach to the 'atomistic' simulation of aggressively scaled sub-0.1 micron MOSFET's. These devices are so small that their characteristics depend on the precise location of dopant atoms within them, not just on their average density. A full-scale three-dimensional drift-diffusion atomistic simulation approach is first described and used to verify more economical, but restricted, options. To reduce processor time and memory requirements at high drain voltage, we have developed a self-consistent option based on a solution of the current continuity equation restricted to a thin slab of the channel. This is coupled to the solution of the Poisson equation in the whole simulation domain in the Gummel iteration cycles. The accuracy of this approach is investigated in comparison to the full self-consistent solution. At low drain voltage, a single solution of the nonlinear Poisson equation is sufficient to extract the current with satisfactory accuracy. In this case, the current is calculated by solving the current continuity equation in a drift approximation only, also in a thin slab containing the MOSFET channel. The regions of applicability for the different components of this hierarchical approach are illustrated in example simulations covering the random dopant-induced threshold voltage fluctuations, threshold voltage lowering, threshold voltage asymmetry, and drain current fluctuations.

Asenov, Asen↗