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At least 1,027 records · Page 57

Silicon carbide thyristor

The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.

Edmond, John A.↗

Channel Temperature Determination for AlGaN/GaN HEMTs on SiC and Sapphire

Numerical simulation results (with emphasis on channel temperature) for a single gate AlGaN/GaN High Electron Mobility Transistor (HEMT) with either a sapphire or SiC substrate are presented. The static I-V characteristics, with concomitant channel temperatures (T(sub ch)) are calculated using the software package ATLAS, from Silvaco, Inc. An in-depth study of analytical (and previous numerical) methods for the determination of T(sub ch) in both single and multiple gate devices is also included. We develop a method for calculating T(sub ch) for the single gate device with the temperature dependence of the thermal conductivity of all material layers included. We also present a new method for determining the temperature on each gate in a multi-gate array. These models are compared with experimental results, and show good agreement. We demonstrate that one may obtain the channel temperature within an accuracy of +/-10 C in some cases. Comparisons between different approaches are given to show the limits, sensitivities, and needed approximations, for reasonable agreement with measurements.

Freeman, Jon C.↗

SiC Optically Modulated Field-Effect Transistor

An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification of the photon-detection signal. A family of operating curves characterizing the OFET can be generated in a series of measurements performed at different intensities of incident ultraviolet light.

Tabib-Azar, Massood↗

Reducing NPR 7120.5D to Practice: Preparing for a Life-Cycle Review

In March 2007, NASA issued revised rules for space flight project management, NPR 7120.5D, 'NASA Space Flight Program and Project Management Requirements.' Central to the new rules was the construct of Key Decision Points, maturity gates that the project team must pass in order to continue development. In order that the KDP decision be fully informed, the NPR required, as entrance criteria for the gate, the generation and delivery of specified planning, technical, and cost/schedule documents (gate products) and a life-cycle review, the Preliminary Design Review. Building on JPL experience on the Prometheus and Juno projects, the team successfully organized for and conducted these reviews on an aggressive schedule. Key actions were taken to proactively interact with the SRB, produce high-quality gate products with stakeholder review, generate review presentation materials, and handle a myriad of supporting logistical functions. A review preparation team was established, including a Review Captain and leads for documentation, information systems, and logistics, and their roles, responsibilities and task assignments were identified. Aids were produced, including a detailed review preparation schedule and a comprehensive gate products production table. Institutional support was leveraged early and often. Implementation strategy reflected the needs of a nationally-distributed team, as well as applicable export control and IT security requirements. This paper gives a brief overview of the GRAIL mission and its project management challenges, provides a detailed description of project PMSR and PDR preparation and execution activities, including positive and negative lessons learned, and identifies recommendations for future NASA (and non-NASA) project teams.

NPR 7120.5D↗

Fingerprinted circuits and methods of making and identifying the same

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Ferguson, Michael Ian↗

Double-Acting, Locking Carabiners

A proposed design for carabiners (tether hooks used in mountaineering, rock climbing, and rescue) is intended to make it possible to operate these devices even while wearing thick gloves. According to the proposal, the gate of a carabiner would be capable of swinging either toward or away from the hook body, relative to the closed position. The gate would be spring-biased to return to the closed position. An external locking collar would be pinned to an internal locking rod that would be springloaded to slide the collar longitudinally over the gate to lock the gate in the closed position. The gate would be unlocked by sliding the collar axially against the spring load. To reduce the probability of inadvertent unlocking, the rod-and-collar mechanism would include two locking buttons. Optionally, the rod-and-collar mechanism could be replaced with an external locking mechanism based on a longer collar.

Chang, Chi-Min↗

Fingerprinted circuits and methods of making and identifying the same

A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit.

Ferguson, Michael Ian↗

Comparison of Different Control Schemes for Strategic Departure Metering

Airports and their terminal airspaces are key choke points in the air transportation system causing major delays and adding to pollution. A solution aimed at mitigating these chokepoints integrates the scheduling of runway operations, flight release from the gates and ramp into the airport movement area, and merging with other traffic competing for downstream airspace points. Within this integrated concept, we present a simulation-based analysis of the departure metering process, which delays the release of flights into the airport movement area while balancing two competing objectives: (1) maintaining large enough queues at the airport resources to maximize throughput and (2) absorbing excess delays at the gates or in ramp areas to save on fuel consumption, emissions, noise, and passenger discomfort. Three metering strategies are compared which respectively attempt to control the number of flights that (1) left the gate but did not take off, (2) left the ramp but did not take off, and (3) spent their unimpeded transit time to the runway but did not take off. It was observed that under deterministic and demand uncertainty conditions, the first strategy performed better than the other two strategies in terms of maintaining the runway throughput while transferring a significant average delay of two minutes to the gate. On the other hand, under uncertainties of flight transit time and runway service rate, all the strategies struggled to delay flights at the gate without a significant impact on the runway throughput.

air traffic management↗

Inrush Current Suppression Circuit and Method for Controlling When a Load May Be Fully Energized

A circuit and method for controlling when a load may be fully energized includes directing electrical current through a current limiting resistor that has a first terminal connected to a source terminal of a field effect transistor (FET), and a second terminal connected to a drain terminal of the FET. The gate voltage magnitude on a gate terminal of the FET is varied, whereby current flow through the FET is increased while current flow through the current limiting resistor is simultaneously decreased. A determination is made as to when the gate voltage magnitude on the gate terminal is equal to or exceeds a predetermined reference voltage magnitude, and the load is enabled to be fully energized when the gate voltage magnitude is equal to or exceeds the predetermined reference voltage magnitude.

Schwerman, Paul↗

Wheels-Off Time Uncertainty Impact on Benefits of Early Call for Release Scheduling

Arrival traffic scenarios with 808 flights from 173 airports to Houston George Bush International airport are simulated to determine if Call For Release flights can receive a benefit in terms of less delay over other flights by scheduling prior to gate pushback (look-ahead in time) as opposed to at gate pushback. Call for Release flights are departures that require approval from Air Route Traffic Control Center prior to release. Realism is brought to the study by including gate departure delay and taxi-out delay uncertainties for the 77 major U. S. airports. Gate departure delay uncertainty is assumed to increase as a function of look-ahead time. Results show that Call For Release flights from an airport within the freeze horizon (a region surrounding the arrival airport) can get an advantage over other flights to a capacity constrained airport by scheduling prior to gate pushback, provided the wheels-off time uncertainty with respect to schedule is controlled to a small value, such as within a three-minute window. Another finding of the study is that system delay, measured as the sum of arrival delays, is smaller when flights are scheduled in the order of arrival compared to in the order of departure. Because flights from airports within the freeze horizon are scheduled in the order of departure, an increase in the number of internal airports with a larger freeze horizon increases system delay. Delay in the given scenario was found to increase by 126% (from 13.8 hours to 31.2 hours) as freeze horizon was increased from 30-minutes to 2-hours in the baseline scenario.

wheels-off time uncertainty↗

Alternatives for Scheduling Departures for Efficient Surface Metering in ATD-2: Exploration in a Human-in-the-Loop Simulation

Human-in-the-Loop (HITL) simulation was conducted to explore the impacts of various surface metering goals on operations and Ramp Controllers at Charlotte Douglas International Airport (CLT). Three conditions were compared: Baseline, with no surface metering, instructions to meet advisory times at the gate only, and instructions to meet advisory times at the gate as well as the times at the scheduled taxiway spot, where aircraft are delivered to Air Traffic Control (ATC). Results showed increased compliance for taxiway spot times when compliance was first met for gate advisories. Instructing Ramp Controllers to meet advisory times at the gate improves spot time compliance and therefore surface scheduling predictability at CLT. Results also demonstrated there was increased compliance overall with gate and spot times in the second condition. This was likely due to higher Ramp Controller workload in the third condition.

Airport surface scheduling↗

Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans

Described herein are various technologies pertaining to randomizing logic associated with dangling nodes in a digital circuit design. A dangling node is an input to or output from a logic gate in the digital circuit design that is identified as not impacting a desired output of the digital circuit design. Randomizing the logic associated with a dangling node can include deleting a logic gate, adding a logic gate, replacing a logic gate with another logic gate, etc. Randomizing the logic associated with the dangling node prevents hardware trojans that may have been inserted into the circuit design from being implemented in a circuit that is generated based upon the design.

97 MATHEMATICS AND COMPUTING↗

Electronic circuit for control or coupling of single charges or spins and methods therefor

A quantum dot structure having a split-gate geometry is provided. The quantum dot is configured for incorporation into a quantum dot array of a quantum processing unit. A gap between a reservoir accumulation gate and a quantum dot accumulation gate provides a tunnel barrier between an electric charge reservoir and a quantum dot well. An electrical potential applied to the gates defines a tunnel barrier height, width and charge tunneling rate between the well and the reservoir without relying on any barrier gate to control the charge tunneling rate.

Pioro-Ladriere, Michel↗

Quantum simulation of $\phi^4$ theories in qudit systems

We discuss the implementation of quantum algorithms for lattice $\Phi^4$ theory on circuit quantum electrodynamics (cQED) system. The field is represented on qudits in a discretized field amplitude basis. The main advantage of qudit systems is that its multi-level characteristic allows the field interaction to be implemented only with diagonal single-qudit gates. Considering the set of universal gates formed by the single-qudit phase gate and the displacement gate, we address initial state preparation and single-qudit gate synthesis with variational methods.

Kurkcuoglu, Doga Murat↗

Design and Development of a Particle Flow Control Mechanism for Particle-Based CSP System Applications

The submission is a two-page extended abstract. Within particle-based Concentrated Solar Power Systems (CSP), particles are the heat transfer medium, and therefore, the heat transfer effectiveness of these systems is reliant on their ability to effectively control particle mass flow rate. The vast majority of approaches for particle flow control in high temperature CSP is based on a slide-gate approach where a gate is linearly actuated across a tear-drop shaped opening. The slide-gate mechanism has a sensitivity of 0.354 g/s-mm, which is defined as the mass flow rate over the position of the gate. In the present work, we have designed and tested a new particle flow control mechanism with the potential for faster response times and different sensitivities than a slide gate approach enabling more control of particle flow.

14 SOLAR ENERGY↗

Fast Sideband Control of a Weakly Coupled Multimode Bosonic Memory

Circuit quantum electrodynamics (cQED) with superconducting cavities coupled to nonlinear circuits like transmons offers a promising platform for hardware-efficient quantum information processing. We address critical challenges in realizing this architecture by weakening the dispersive coupling while also demonstrating fast, high-fidelity multimode control by dynamically amplifying gate speeds through transmon-mediated sideband interactions. This approach enables transmon-cavity SWAP gates, for which we achieve speeds up to 30 times larger than the bare dispersive coupling. Combined with transmon rotations, this allows for efficient, universal state preparation in a single cavity mode, though achieving unitary gates and extending control to multiple modes remains a challenge. In this work, we overcome this by introducing two sideband control strategies: (1) a shelving technique that prevents unwanted transitions by temporarily storing populations in sideband-transparent transmon states and (2) a method that exploits the dispersive shift to synchronize sideband transition rates across chosen photon-number pairs to implement transmon-cavity SWAP gates that are selective on photon number. We leverage these protocols to prepare Fock and binomial code states across any of ten modes of a multimode cavity with millisecond cavity coherence times. We demonstrate the encoding of a qubit from a transmon into arbitrary vacuum and Fock state superpositions, as well as entangled NOON states of cavity mode pairs— a scheme extendable to arbitrary multimode Fock encodings. Furthermore, we implement a new binomial encoding gate that converts arbitrary transmon superpositions into binomial code states in $\qty{4}{\micro\second}$ (less than $1/\chi$), achieving an average post-selected final state fidelity of $\qty{96.3}{\percent}$ across different fiducial input states.

Huang, Jordan [Rutgers U., Piscataway]↗

Universal Jaynes-Cummings Control of an Oscillator

The Jaynes-Cummings (JC) interaction-the coherent exchange of excitations between a two-level system and a harmonic oscillator-is one of the fundamental interactions of quantum optics, realized across platforms such as cavity quantum electrodynamics, trapped ions, mechanical resonators, and superconducting circuits. Although JC interactions and qubit rotations form a universal gate set for oscillator control, practical implementations have not been demonstrated. Here we develop and experimentally demonstrate universal JC-based oscillator control by compiling arbitrary unitary gates into sequences of JC interactions and qubit rotations. In our experiment, the oscillator is realized using a mode of a high quality factor microwave cavity and the ancilla qubit using a superconducting transmon circuit, with the JC interaction implemented by a sideband interaction enabled by the Josephson nonlinearity. The native gates are constructed to be closed below a chosen cutoff photon number, encoding a qudit with suppressed leakage errors, while ancilla relaxation errors are detectable. We further find that the dispersive shift serves as a compilation resource that reduces circuit depths. We demonstrate universal qudit control and implement a single-qutrit gate set with a mean post-selected process fidelity of 96%, as well as ququart and ququint shift gates. These results establish Jaynes-Cummings control as a practical route to universal oscillator control, enabling programmable bosonic processors across a variety of quantum platforms.

Huang, Jordan [Rutgers U., Piscataway]↗

Progress and Challenges for Memtransistors in Neuromorphic Circuits and Systems

Due to the increasing importance of artificial intelligence (AI), significant recent effort has been devoted to the development of neuromorphic circuits that seek to emulate the energy-efficient information processing of the brain. While non-volatile memory (NVM) based on resistive switches, phase-change memory, and magnetic tunnel junctions has shown potential for implementing neural networks, additional multi-terminal device concepts are required for more sophisticated bio-realistic functions. Of particular interest are memtransistors based on low-dimensional nanomaterials, which are capable of electrostatically tuning memory and learning behavior at the device level. Herein, a conceptual overview of the memtransistor is provided in the context of neuromorphic circuits. Recent progress is surveyed for memtransistors and related multi-terminal NVM devices including dual-gated floating-gate memories, dual-gated ferroelectric transistors, and dual-gated van der Waals heterojunctions. Further, the different materials systems and device architectures are classified based on the degree of control and relative tunability of synaptic behavior, with an emphasis on device concepts that harness the reduced dimensionality, weak electrostatic screening, and phase-changes properties of nanomaterials. Finally, strategies for achieving wafer-scale integration of memtransistors and multi-terminal NVM devices are delineated, with specific attention given to the materials challenges for practical neuromorphic circuits.

36 MATERIALS SCIENCE↗